LLVM 11.0 - AshokBhat/notes GitHub Wiki

Core support

  • AArch64: Added support for Cortex-A34, Cortex-A77, Cortex-A78 and Cortex-X1 cores.
  • Arm : Added support for Cortex-M55, Cortex-A77, Cortex-A78 and Cortex-X1 cores.

SVE/2

Scalable IR support

LLVM IR now supports two distinct llvm::FixedVectorType and llvm::ScalableVectorType vector types, both derived from the base class llvm::VectorType. A number of algorithms dealing with IR vector types have been updated to make sure they work for both scalable and fixed vector types. Where possible, the code has been made generic to cover both cases using the base class. Specifically, places that were using the type unsigned to count the number of lanes of a vector are now using llvm::ElementCount. In places where uint64_t was used to denote the size in bits of a IR type we have partially migrated the codebase to using llvm::TypeSize.

ACLE support

Implemented codegen support for the SVE C-language intrinsics documented in Arm C Language Extensions (ACLE) for SVE (version 00bet5). For more information, see the clang 11 release notes. What works in LLVM 11:

  • __ARM_FEATURE_SVE (Base SVE functions defined in ACLE specification, section 6)
  • __ARM_FEATURE_SVE_BF16 (BFloat16 extensions, section 7.2)
  • __ARM_FEATURE_SVE_MATMUL_INT8 (int8 matrix multiply extensions, section 7.3)
  • __ARM_FEATURE_SVE_MATMUL_FP32 (fp32 matrix multiply extensions, section 7.4)
  • __ARM_FEATURE_SVE_MATMUL_FP64 (fp64 matrix multiply extensions, section 7.5)
  • __ARM_FEATURE_SVE2 (base SVE2 functions , section 8 )
  • __ARM_FEATURE_SVE2_BITPERM (SVE2 bit permutation extensions, section 9.2)
  • __ARM_FEATURE_SVE2_AES (SVE2 AES-128 extensions, section 9.3)
  • __ARM_FEATURE_SVE2_SHA3 (SVE2 SHA3 extensions, section 9.4)
  • __ARM_FEATURE_SVE2_SM4 (SVE2 SM4 extensions, section 9.5)

Matrix Multiply extension

  • AArch64: Assembly and intrinsics support for the Armv8.6-A Matrix Multiply extension for Neon and SVE vectors.
  • Arm: Assembly and intrinsics support for the Armv8.6-A Matrix Multiply extension for Neon vectors.

BF16 extension

  • AArch64: Support for the ARMv8.2-BF16 BFloat16 extension. This includes a new C-level storage-only __bf16 type, a BFloat IR type, a bf16 MVT, and assembly and intrinsics support.
  • Arm: Support for the ARMv8.2-AA32BF16 BFloat16 extension. This includes a new C-level storage-only __bf16 type, a BFloat IR type, a bf16 MVT, and assembly and intrinsics support.

Other features announced as part of 2019 architecture extensions

Assembly support for the following extensions:

  • Enhanced Counter Virtualization (ARMv8.6-ECV).
  • Fine Grained Traps (ARMv8.6-FGT).
  • Activity Monitors virtualization (ARMv8.6-AMU).
  • Data gathering hint (ARMv8.0-DGH).

Misc

AArch64

  • Back up and restore x18 in functions with windows calling convention on non-windows OSes.
  • AArClearly error out on unsupported relocations when targeting COFF, instead of silently accepting some (without being able to do what was requested).

AArch32

  • The Machine Outliner is now supported for ARM and Thumb2, it is not turned on by default and can be enabled with the -moutline clang flag.
  • Clang now defaults to -fomit-frame-pointer when targeting non-Android Linux for arm and thumb when optimizations are enabled. Users that were previously not specifying a value and relying on the implicit compiler default may wish to specify -fno-omit-frame-pointer to get the old behavior. This improves compatibility with GCC.
  • Added support for CMSE.

Arm v8.1-M MVE instruction set

  • Implemented C-language intrinsics for the full Arm v8.1-M MVE instruction set. <arm_mve.h> now supports the complete API defined in the Arm C Language Extensions.

Custom Datapath Extension (CDE)

  • Added support for assembly for the optional Custom Datapath Extension (CDE) for Arm M-profile targets.
  • Implemented C-language intrinsics <arm_cde.h> for the CDE instruction set.

CMSE support

  • CMSE is an extension to the C language that can be implemented by tool vendors to provide toolchain support for Secure executable files that are written in the C language. Non-secure executable files do not require any additional toolchain support.
  • The <arm_cmse.h> header must be included before using CMSE support, except for using the __ARM_FEATURE_CMSE macro.
  • Bits 0 and 1 of feature macro __ARM_FEATURE_CMSE are set if CMSE support for Secure executable files is available.
  • Availability of CMSE implies availability of the TT instruction.
  • A compiler might provide a switch to enable support for creating CMSE Secure executable files. ARM recommends such a switch to be named -mcmse

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