ARMv8.1 A - AshokBhat/notes GitHub Wiki

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  • Key features - ARMv8.1-LSE (atomics)

Arm Architecture

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Timeline

In December 2014, ARMv8.1-A an update with "incremental benefits over v8.0", was announced.

Changes

The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.

Instruction set changes

Instruction set enhancements included the following:

  • A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions.

ARMv8.1-LSE, Armv8.1 Large System Extensions

ARMv8.1-LSE introduces a set of atomic instructions:

  • Compare and Swap instructions, CAS and CASP.
  • Atomic memory operation instructions, LD<OP> and ST<OP>, where <OP> is one of ADD, CLR, EOR, SET, SMAX, SMIN, UMAX, and UMIN.
  • Swap instruction, SWP.

Only added to the A64 instruction set. Mandatory in Armv8.1 implementations.

ARMv8.1-RDMA, Armv8.1 Advanced SIMD instructions

ARMv8.1-RDMA introduces Rounding Double Multiply Add/Subtract Advanced SIMD instructions.

A64 instruction set additions

  • SQRDMLAH (by element)
  • SQRDMLAH (vector)
  • SQRDMLSH (by element)
  • SQRDMLSH (vector)

T32 and A32 instruction set additions

  • VQRDMLAH
  • VQRDMLSH

Mandatory in Armv8.1 implementations.

CRC instruction changes

  • The optional CRC instructions in v8.0 become a requirement in ARMv8.1.

Exception model and memory translation system changes

Enhancements for the exception model and memory translation system included the following:

  • An increased VMID range for virtualization; supports a larger number of virtual machines.
  • Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism.
  • A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS.

Privileged Access Never (PAN)

  • A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled.

Virtualization Host Extensions (VHE)

  • These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems.
  • The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.