TEI0022 CC block diagrams - ArrowElectronics/data-storm-daq GitHub Wiki
The Trenz TEI0022 board contains 2 FPGA devices and many peripheral devices. The Primary FPGA is the Cyclone V SoC and the MAX10 FPGA has a support role in monitoring power rails, reading push buttons, driving LED's, and optionally configuring the Cyclone V SoC.


- SE Processor:
- Single or Dual ARM Cortex® A9 MPU
- Up to 925 MHz max clock speed
- 32KB L1 Program Cache (per core)
- 32KB L1 Data Cache (per core)
- 512 KB L2 Cache (shared)
- 181 HPS I/O pins
- 1 Hard Memory Controller (LPDDR2, DDR2, DDR3)
- FPGA Fabric:
- Up to 110K Logic Elements (LE)
- Up to 5.5Mb M10K Memory
- Up to 621Kb MLAB Memory
- Up To 112 Variable Precision DSP blocks
- Up to 224 18x18 multipliers
- Up to 288 User FPGA I/O pins
- 1 Hard Memory Controller (LPDDR2, DDR2, DDR3)
FPGA DDR3
HPS DDR3
FMC LPC Connector
PMOD x4
microSD Card Connector
Ethernet PHY
RJ-45 Ethernet Connector
USB PHY
USB HUB
dual USB-A Connector
HDMI Transmitter
HDMI Connector
Intel MAX10
micro-USB to UART Interface
USB to JTAG and UART
micro-USB to JTAG and UART Connector
SMA Connector
Push Button
LED
4-bit DIP Switch
12 VDC Power Jack
Clock Generator
Programmable Clock Generator
QSPI for HPS
QSPI for FPGA
Temperature Sensor
EEPROM