TEI0022 Build HDL - ArrowElectronics/data-storm-daq GitHub Wiki

Introduction

This section describes how to download the design files needed from the github repository and create the GHRD project from the ground up.

Files needed:

File Description
system_top.v top-level Verilog file
tei0022_system_assign.tcl Pin Assignment
system_constr.sdc Timing Constraints

Building the GHRD Project

Create the project framework

  • Open Quartus® 18.1

  • Use the New Project Wizard to create a new project.

  • Set up the Project’s working directory (no spaces in folder or project names), Project Name to be system_top, and click Next.

  • On the next screen select Empty project and click Next.
  • On the next Add Files screen, click Next without adding files.
  • On the next screen, select a device. Use the filtering boxes or scroll through the list of available Cyclone® V SE Mainstream devices to arrive at the 5CSEMA5F31C8 and select it then click Next, then Finish.

Create the Processor System using Platform Designer

  • Open Platform Designer from Quartus via one of the 2 methods below:
    • Tools -> Platform Designer menu, or
    • Click on its icon in the tool bar. A blank project is created with a default name of unsaved.qsys.
  • Do a File -> Save As … to give it the name system_bd.

Add peripheral modules from the IP Catalog

Add the HPS IP

Either type HPS in the IP Catalog search bar or, expand the Processors and Peripherals -> Hard Processor Systems and double-click Arria V/Cyclone V Hard Processor System to add it to the system.

This action opens the HPS configuration window.

  • In the FPGA Interfaces tab,
    • un-check all boxes.
    • Leave the AXI Bridges set to their defaults.
    • In the FPGA-to-HPS SDRAM Interface section do:
      • Change f2h_sdram0 type to be Avalon-MM Bidirectional and keep it 64-bit.
      • Use the ‘+’ to add 2 more interfaces: f2h_sdram1 and f2h_sdram2 as type AXI-3 64-bit.
  • In the Interrupts section, check the box to Enable FPGA-to-HPS interrupts.
  • Select the Peripheral Pins tab and set the peripheral pins as follows:
    • Ethernet Media Access Controller: EMAC1 pin to HPS I/O Set 0, EMAC1 mode to RGMII.
    • Quad SPI Flash Controller: QSPI pin to HPS I/O set 0, QSPI mode to 1SS.
    • SD/MMC Controller: SDIO pin to HPS I/O Set 0, SDIO mode to 4-bit Data.
    • USB Controller: USB1 pin to HPS I/O Set 0, USB1 PHY interface mode to SDR with PHY clock output mode.
    • UART Controller: UART0 pin to HPS I/O set 0, UART0 mode to No Flow Control.
    • I2C Controller: I2C0 pin to HPS I/O Set 1, I2C1 pin to HPS I/O Set 0.
  • Scroll down to the bottom of the Peripheral Pins window until the Peripheral Mux Table is visible.
    • Scroll the table to the right until the GPIO column is visible and click the following pins:
      • GPIO00, GPIO09, GPIO35, GPIO40-44, GPIO48, GPIO53-59, GPIO61, GPIO65.
  • Select the HPS Clocks tab and keep all settings in the Input Clocks sub-tab at defaults.
  • Select the Output Clocks sub-tab and change the following selections from their defaults:
    • In the Main PLL Output Clocks section, change the Configuration/HPS-to-FPGA user 0 clock frequency to 80.0 MHz,
    • In the HPS-to-FPGA User Clocks section,
      • check the boxes for Enable HPS-to-FPGA user 0 clock, Enable HPS-to-FPGA user 1 clock, and Enable HPS-to-FPGA user 2 clock,
      • change the user 2 clock frequency to 133.333 MHz.
  • Select the SDRAM tab.
    • In the PHY Settings sub-tab, set the Memory clock frequency to 333.3 MHz, the PLL reference clock frequency to 25MHz.
  • Select the Memory Parameters sub-tab.
    • Set the Memory device speed grade to 800.0 MHz,
    • Set Total interface width to 32 which will automatically update the Number of DQS groups to 4.
    • Set Row address width to 16,
    • Set Column address width to 10,
    • Set Memory CAS latency setting to 5,
    • Set ODT Rtt nominal value to RZQ/6,
    • Set Memory write CAS latency setting to 5.
  • Select the Memory Timing sub-tab and set the values as show in the figure below:
  • Select the Board Settings sub-tab.
    • In the Board Skews section change the setting to match the figure below:
  • Click Finish.

In the System Contents tab do the following:

  • Rename the clk_0 module to sys_clk by right click the name -> Rename,
  • Rename the hps_0 module to sys_hps,
  • Double-click in the memory row Export column and call it sys_hps_memory,
  • Double-click in the hps_io row Export column and call it sys_hps_hps_io,
  • Double-click in the h2f_reset row Export column and call it sys_hps_h2f_reset,
  • Double-click in the sys_clk/clk_in Export column and rename it sys_clk,
  • Double-click in the sys_clk/clk_in_reset Export column and rename it sys_rst,
  • Connect the h2f_user0_clock to the h2f_axi_clock, f2h_axi_clock, and 2f_lw_axi_clock.

Add the HDMI IP

The HDMI interface requires multiple IP cores from the IP Catalog.

- Add DMA Clock IP

  • Find the Clock Source IP in the IP Catalog,
  • Double-click it to add it to the System Contents widow,
  • Keep the default settings,
  • Click Finish,
  • Rename it sys_dma_clk,
  • Connect its clk_in port to the h2f_user0_clock spine,
  • Connect its clk_in_reset port to the sys_clk/clk_reset port,
  • Connect its clk port to the sys_hps/f2h_sdram2_clock and sys_hps/f2h_sdram1_clock ports.

- Add HDMI PLL IP

  • Find the PLL Intel FPGA IP in the IP Catalog,
  • Double click it to add it to the System Contents.
  • In the wizard, make the following settings:
    • In the General tab, change the Reference Clock Frequency to 80.0 MHz,
    • Un-check the Enable locked output port,
    • Change the outclk0 Desired Frequency to 74.25 MHz,
    • Click Finish.
  • Rename it hdmi_pll,
  • Connect its refclk port to the h2f_user0_clock spine,
  • Connect its reset port to the clk_reset spine,
  • Connect its outclk0 port to the sys_hps/f2h_sdram0_clock port.

- Add HDMI Clock IP

  • Find the Clock Source in IP Catalog,
  • Double click it to add it to the *System Contents.
  • In the wizard, change the Clock frequency to 74250000 Hz,
  • Click Finish.
  • Rename it hdmi_clock_out,
  • Connect its clk_in to the hdmi_pll/outclk0 port,
  • Double-click in the export column of the clk port row and name it hdmi.

- Add HDMI Frame Buffer IP

  • Find the Frame Buffer II (4K Ready) in the IP Catalog,
  • Double click it to add it to the System Contents,
  • In the wizard, make the following settings and click Finish:

    • In the Video data Format section do:

      • Set Maximum frame width: to 1280,
      • Set Maximum frame height: to 720,
      • Set Bits per color sample: to 8,
      • Set Number of color planes: to 4.

    • In the Memory section, do:

      • Un-check the box for Use separate clock for the Avalon master interface,
      • Set Avalon port width to 128.

    • In the Frame Configuration section, do:

      • Check the box for Module is Frame Reader only,
      • Check the box for **Frame dropping,
      • Check the box for Frame repeating.

    • In the Control section, check the box for Run-time reader control.

  • Rename it hdmi_frame_reader.
  • Connect its main_clock port to the hdmi_pll/outclk0 port.
  • Connect its main_reset port to the sys_clk/clk_reset spine.
  • Connect its control_interrupt port to the *sys_hps/f2h_irq0 port and assign it number 4 in the IRQ column.
  • Connect its control port to the sys_hps/h2f_lw_axi_master port.
  • Connect its mem_master_rd port to the sys_hps/f2h_sdram0_data port.

- Add HDMI out data IP

  • Find the Clocked Video Output II (4K Ready) in the IP Catalog.
  • Double-click it to add it to the System Contents.
  • In the wizard, make the following settings and click Finish:
    • Set the Image Data Format parameters to 1280/720/8/4.
    • Set the Separate Sync Only – Frame / Field 1 parameters to 40/220/110/5/5/20.
  • Rename it hdmi_out_data.
  • Connect its main_clock port to the hdmi_pll/outclk0 port.
  • Connect its main_reset to the sys_clk/clk_reset spine.
  • Connect its din port to the hdmi_frame_reader/dout port.
  • Double-click in the Export column of the clocked_video row and name it hdmi_out_data.

Add the System ID Peripheral IP

-Find the System ID Peripheral in the IP Catalog.

  • Double-click it to add it to the System Contents.
  • In the wizard, make the following settings and change the 32 bit System ID parameter to 0xacd51302.
  • Click Finish.
  • Rename it sys_id.
  • Connect its clk port to h2f_user0_clock spine.
  • Connect its reset port to the sys_clk/clk_reset spine.
  • Connect its control_slave port to the sys_hps/h2f_lw_axi_master port.

Conclude settings in Platform Designer

From the Platform Designer menu bar, select System -> Assign Base Addresses.

If there are no messages in red color, do:

  • Click the Generate HDL button in the bottom right of the window,
  • Click Generate in the Generation window that pops up,
  • Click Close in the Save System window,
  • Click Close when the Generate window finishes.

Top-Level design

Import the top-level files using the Quartus Prime window using Project -> Add/Remove Files in project …,

  • Navigate to the folder you placed the 3 required files in, and add the /system_top.v,
  • Add the system_bd.qip located in /system_bd/synthesis/,
  • Add the timing constraints file /system_constr.sdc
  • Click OK in the Settings window.

The top level requires a 12-bit DDIO element.

  • Select the IP Catalog from the tool bar.
  • Search for DDIO and double-click the ALTDDIO_OUT,
  • Give it the name ddr12 and Click OK.
  • In the MegaWizard, set the width to 12 and click Finish.

  • Perform the Analysis & Synthesis step to be able to add pin assignments,

  • Open a Tcl Console in Quartus Prime by View -> Utility Windows -> Tcl Console,

    • At the tcl prompt, source the /tei0022_system_assign.tcl

  • Finish compiling the project by pressing the Start Compilation symbol .

GHRD Block diagram


Next - Build Linux / Devicetree

Return to Build the TEI0022 GHRD

Please click Here to purchase platform boards

⚠️ **GitHub.com Fallback** ⚠️