Run the no‐OS Demonstration Standalone (AD469x) - ArrowElectronics/data-storm-daq GitHub Wiki

In addition to the DataStorm DAQ development kit running either in standalone hardware configuration or remote configuration via an Ethernet cable, it can also run no-OS baremetal software while being connected to a PC via a USB cable.

Configuration for no-OS software access

The AD469x demonstration uses AD4696® Evaluation Platform in this configuration which is comprised of the following components:

Configure BOOTSEL DIP Switches

Select the SD card as the boot source for the processor.

Configure FMC_VADJ DIP Switches

The FMC_VADJ power rails provide power to the EVAL-AD4696FMCZ via the FMC interface. This is an adjustable voltage. It must be set to 3.3V. Modify the VID_SW DIP switch settings to select 3.3V.

Assemble the Hardware

Follow the steps in the order shown below.

  • Insert the Micro SD card into the SD card slot
  • Insert the EVAL-AD4696FMCZ FMC connector into the FMC mating connector on the DataStorm DAQ board
  • Connect the Micro USB cable between the serial port of the DataStorm DAQ board and the host PC.
  • Connect the Signal Generator to the EVAL-AD4696FMCZ SMA connectors
  • Ensure that Jumper JP11 is at position B to give onboard 5V reference, Jumper JP8 is in position A to give VADJ from FMC connector, Jumper JP7 is in position A to supply LDOin with AVDD.
  • Connect the power supply to the DataStorm DAQ
  • Plug the AC-DC adapter into an AC outlet

Signal Source

AD469x is sixteen channel multiplexed ADC, but on EVAL-AD4696FMCZ has only two channel viz ch0 and ch1 is available to give a external signal source. rest of the channel from ch2 to ch15 is given a onboard fixed dc supply. For details refer product link. For channel ch0 and ch1 expects a differential signal but chx(-) channel is effectively grounded on EVAL-AD4696FMCZ. So EVAL-AD4696FMCZ ch0 and ch1 requires a signal within range of 0V to Vref i.e 5V , negative supply signal need to be bias or offset to make in range of 0-5V signal.

The Analog Discovery 2 is used as a signal generator to drive the AD469x input.

Install (if not already done) the Digilent WaveForms App.

Open the WaveForms App and Click on Wavegen in the left margin which opens a waveform window

Click on Channels and select 1
Select Type as Sine
Select Frequency or Period
Set Amplitude to 1V
Set Offset to 1V
Click Run All

Run the no-OS demonstration

Software for no-OS access

There are a few software components that need to be installed in order to run this demo successfully:

  1. A SW terminal like Tera Term VT or Putty

Connect to the target terminal

Run the demonstration

Simply power up the unit. No additional configuration is required. The bare metal application runs automatically and continuously streams analog measurement results across the serial port to be received and displayed in the terminal program running on the separate Windows PC.

ADC Data Mode in HDL

The data_mode variable shown below will configure no-OS program to sample data in either staggered mode or continuous mode. This configuration is internal to the FPGA HDL design.

NOTE: The following example has been configured on AD4696 with outputs available from all 16 channels by default, which can be enabled in either Staggered or Continuous data modes.

Staggered Mode Output

Setting the data_mode variable to 0 makes the data sample in a staggered manner. Internal HDL design will collect and send the data directly to the DMA and will not wait for progression cycle to complete. The next value of the respective channel will be updated in its next sequence only. Thus, the output on the terminal will be in a staggered manner. The length of step will depend on the number on other channels enabled (set to all 16 by default in the no-OS program) between the required channel. This mode supports both Standard Sequencer (STD_SEQ_CONFIG) and Advanced Sequencer data capture. Selecting any disabled channel will give the last state value from that corresponding channel in the terminal.

Continuous Mode Output

Setting data_mode variable to 1 sets data sampling in the continuous mode. Internal HDL design will collect and buffer the ADC data till all enabled channel data is received in one progression cycle. It will then send the buffered data collectively to the DMA. Output on the terminal will be in a continuous data read. This mode only supports the STD_SEQ_CONFIG (Standard Sequencer) enabled and selecting any disabled channel will give output value as 0xdead from that corresponding channel in the terminal.

Return to AD469x Quick Start Guide