Datastorm DAQ GHRD modify top - ArrowElectronics/data-storm-daq GitHub Wiki

Now that the spi_engine has been added in the lower level system_bd, its I/O pins need to be added to the instantantiation and the top-level I/O ring. If the Quartus project is not already open, follow the next two steps:

• Open Quartus® 20.1

    $ ~/intelFPGA_lite/20.1/quartus/bin/quartus &
  

• Use the New Project Wizard to create a new project.

    File --> Open Project
    Enter the path to the project file /home/soceds/datastorm_daq/hdl/projects/arrow_ghrd/tei0022/partial_source/system_top.qpf
  

• Open the system_top.v in Quartus and look for "uncomment",

• Search for the 2 commented sections. Remove the lines containing "/*" and "*/",

• Save the file

• Before pin assignment can be done, the design has to at least be analyzed. To do so, perform the Analysis & Synthesis by pressing the symbol,

• After the above step is completed, Open a Tcl Console in Quartus Prime by selecting View -> Utility Windows -> Tcl Console,

• At the tcl prompt, type (or copy and paste from here) to run the Tcl script which assigns the FPGA pins

• Finish compiling the project by pressing the Start Compilation symbol . A % completion status can be observed in the bottom right corner of the Quartus window.