Datastorm DAQ GHRD hdmi - ArrowElectronics/data-storm-daq GitHub Wiki

AXI_HDMI_TX IP core

The axi_hdmi_tx IP is used to interface to the ADV7511 display driver on the TEI0022 board.

Features

  • AXI based configuration
  • Supports multiple resolution (max 1080p)
  • Video transmission on 36, 24 and 16 bits
  • Supports embedded sync (16bit data)
  • YCbCr or RGB color space output
  • Data clipping (min. and max. for each chroma/color value)

Block Diagram

Configuration Parameters

Name Description Default Value
ID Core ID should be unique for each axi_hdmi_tx IP in the system 0
DEVICE_TYPE 1 = Intel 5 series devices 0
CR_CB_N Used in the chroma subsampling process, selecting which of the red or blue data components will be transmitted first in-between green samples. 1 = red, 0 = blue 0
INTERFACE Interface type towards the 7511. Available options: 16_BIT, 24_BIT, 36_BIT, 16_BIT_EMBEDDED_SYNC 16-bit
OUT_CLK_POLARITY 0 = Launch on rising edge, 1 = Launch on falling edge 0


Interfaces

Interface Pin Type Description
HDMI common interfaces part HDMI interface signals (LVCMOS)
hdmi_clk input pixel clock, generated by an axi_clkgen IP core (axi_hdmi_clkgen in reference design)
hdmi_out_clk output Output Clock
16-bit interface HDMI 16-bit data interface signals (LVCMOS)
hdmi_16_hsync output horizontal sync signal
hdmi_16_vsync output vertical sync signal
hdmi_16_data_e output data enable signal
hdmi_16_data output [15:0] hdmi data
16-bit ES interface HDMI 16-bit data Embedded Sync interface signals (LVCMOS)
hdmi_16_es_data output [15:0] hdmi embedded sync data
24-bit interface HDMI 24-bit data interface signals (LVCMOS)
hdmi_24_hsync output horizontal sync signal
hdmi_24_vsync output vertical sync signal
hdmi_24_data_e output data enable signal
hdmi_24_data output [23:0] hdmi data
36-bit interface HDMI 36-bit data interface signals (LVCMOS)*
hdmi_36_hsync output horizontal sync signal
hdmi_36_vsync output vertical sync signal
hdmi_36_data_e output data enable signal
hdmi_36_data output [35:0] hdmi data
DMA AXIS interface DMA interface
vdma_clk input DMA clock signal
vdma_end_of_frame input AXIS TLAST signal. End of frame indicator.
vdma_valid input AXIS TVALID signal. Data enable signal.
vdma_data input [63:0] AXIS TDATA signal.
vdma_ready output AXIS TREADY signal.
s_axi AXI Memory Map interface

Detailed description

The top module (axi_hdmi_tx), instantiates:

  • axi_hdmi_tx_core module
  • axi_hdmi_tx_vdma module
  • the HDMI TX register map
  • the AXI handling interface

In axi_hdmi_tx_core module the video information is manipulated by passing through several processing blocks (see Block Diagram):

  • CSC (Color Space Converter) –converts the video information from RGB color space to YCbCr color space. If RGB is the desired output color space the CSC block can be bypassed by setting to 1 the value of CSC_BYPASS register.
  • Data Clipping bloc gives the possibility of limiting the minimum and maximum color range values. This block is controlled by FULL_RANGE, REG_CLIPP_MAX and REG_CLIPP_MIN registers.
  • Chroma subsampling block as its name suggests, samples the video information to obtain a video information that requires less bandwidth and has a minimum impact on the video quality experienced by human eyes.
  • Embedded Sync module interleaves the video synchronization signals with the video information, obtaining a more compact transmission path.
  • Sync Signals block is responsible for generating the video synchronization signals for video resolutions written in HDMI interface Control register. The axi_hdmi_tx_vdma module ensures the clock domain crossing circuit between the video source, typically a DMAC core and the axi_hdmi_core, which works at different clock speeds depending on the required resolution.

Register Map

DWORD BYTE Bits Name Type Default Description
0x0010 0x0040 REG_RSTN HDMI Interface Control & Status
[0] RSTN RW 0
0x0011 0x0044 REG_CNTRL1 HDMI Interface Control & Status
[2] SS_BYPASS RW 0 If set (0x1) bypasses the chroma sub-sampler. This is primarily intended to be used to send the test-pattern directly to the HDMI transmitter without modifying it.
[1] RESERVED RO 0 Reserved
[0] CSC_BYPASS RW 0 If set (1) bypasses color space conversion (if equipped). And depending on its value, the default value of color space boundaries is set in the REG_CLIPP_MAX and REG_CLIPP_MIN registers.
0x0012 0x0048 REG_CNTRL2 HDMI Interface Control & Status
[1:0] SOURCE_SEL RW 0x0 Select the HDMI data source- register constant (0x3), incr-pattern (0x2), input (0x1) or disabled (0x0).
0x0013 0x004C REG_CNTRL3 HDMI Interface Control & Status
[23:0] CONST_RGB RW 0x000000 This is the RGB value transmitted, if the source is constant (see above).
0x0015 0x0054 REG_CLK_FREQ HDMI Interface Control & Status
[31:0] CLK_FREQ RO 0x000000 Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016 0x0058 REG_CLK_RATIO HDMI Interface Control & Status
[31:0] CLK_RATIO RO 0x000000 Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017 0x005C REG_STATUS HDMI Interface Control & Status
[0] STATUS RO 0 Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018 0x0060 REG_VDMA_STATUS HDMI Interface Control & Status
[1] VDMA_OVF RW1C 0 If set, indicates vdma overflow.
[0] VDMA_UNF RW1C 0 If set, indicates vdma underflow.
0x0019 0x0060 REG_TPM_STATUS HDMI Interface Control & Status
[1] HDMI_TPM_OOS RW1C 0 If set, indicates TPM OOS at the HDMI interface.
[0] VDMA_TPM_OOS RW1C 0 If set, indicates TPM OOS at the VDMAinterface.
0x001A 0x0068 REG_CLIPP_MAX HDMI Interface Control & Status
[23:16] R_MAX/Cr_MAX RW 0xF0 Defines the maximum value for clipping the red or red-difference chroma component. Default value are 0xF0 for red-difference chroma and 0xFE for red.
[16:8] G_MAX/Y_MAX RW 0xEB Defines the maximum value for clipping the green or luma component. Default values are 0xEB for luma and and 0xFE for green.
[7:0] B_MAX/Cb_MAX RW 0xF0 Defines the maximum value for clipping the blue or blue-difference chroma component. Default value are 0xF0 for blue-difference chroma and 0xFE for blue.
0x001B 0x006C REG_CLIPP_MIN HDMI Interface Control & Status
[23:16] R_MIN/Cr_MIN RW 0x10 Defines the maximum value for clipping the red or red-difference chroma component. Default value are 0x10 for red-difference chroma and 0x01 for red.
[16:8] G_MIN/Y_MIN RW 0x10 Defines the maximum value for clipping the green or luma component. Default values are 0x10 for luma and and 0x01 for green.
[7:0] B_MIN/Cb_MIN RW 0x10 Defines the maximum value for clipping the blue or blue-difference chroma component. Default value are 0x10 for blue-difference chroma and 0x01 for blue.
0x0100 0x0400 REG_HSYNC_1 HDMI Interface Control & Status
[31:16] H_LINE_ACTIVE RW 0x0000 This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p)
[15:0] H_LINE_WIDTH RW 0x0000 This is the horizontal line width (no. of pixel clocks per line). e.g. 2200 (1080p)
0x0101 0x0404 REG_HSYNC_2 HDMI Interface Control & Status
[15:0] H_SYNC_WIDTH RW 0x0000 This is the horizontal sync width (no. of pixel clocks). e.g. 44 (1080p)
0x0102 0x0408 REG_HSYNC_3 HDMI Interface Control & Status
[31:16] H_ENABLE_MAX RW 0x0000 This is the horizontal data enable maximum. It is the sum of H_ENABLE_MIN and the active pixel width. e.g. 2112 (192 + 1920) (1080p)
[15:0] H_ENABLE_MIN RW 0x0000 This is the horizontal data enable minimum. It is the sum of horizontal back porch (number of clock cycles between the falling edge of HSYNC to the rising edge of DE) and the sync width. e.g. 192 (44 + 148) (1080p)
0x0110 0x0440 REG_VSYNC_1 HDMI Interface Control & Status
[31:16] V_FRAME_ACTIVE RW 0x0000 This is the vertical frame active line width (active resolution height). e.g. 1080 (1080p)
[15:0] V_FRAME_WIDTH RW 0x0000 This is the vertical frame width (no. of lines per frame). e.g. 1125 (1080p)
0x0111 0x0444 REG_VSYNC_2 HDMI Interface Control & Status
[15:0] V_SYNC_WIDTH RW 0x0000 This is the vertical sync width (no. of lines). e.g. 5 (1080p)
0x0112 0x0448 REG_VSYNC_3 HDMI Interface Control & Status
[31:16] V_ENABLE_MAX RW 0x0000 This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active pixel height. e.g. 1121 (41 + 1080) (1080p)
[15:0] V_ENABLE_MIN RW 0x0000 This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines between the falling edge of VSYNC to the rising edge of DE) and the sync width. e.g. 41 (36 + 5) (1080p)
Access Type Name Description
RO Read-only Reads will return the current register value. Writes have no effect.
RW Read-write Reads will return the current register value. Writes will change the current register value.
RW1C Write-1-to-clear Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written.

Design considerations

Additional IPs needed:

  • axi_dmac
  • axi_clkgen
  • axi_spdif_tx

High-Speed DMA Controller Peripheral (axi_dmac) provides a high-bandwidth direct memory access for the video stream. The core is configured as follows:

  ad_ip_instance axi_dmac axi_hdmi_dma
  ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_SRC 0
  ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_DEST 1
  ad_ip_parameter axi_hdmi_dma CONFIG.CYCLIC true
  ad_ip_parameter axi_hdmi_dma CONFIG.DMA_2D_TRANSFER true
  ad_ip_parameter axi_hdmi_dma CONFIG.DMA_DATA_WIDTH_DEST 64

The audio path is separated from the video path, for audio resources:fpga:docs:axi_spdif_tx core https://github.com/analogdevicesinc/hdl/tree/master/library/axi_spdif_tx) is needed to transmit the audio information to the ADV7511 device. The whole system needs to be controlled by a processor (ARM or a soft core) that can programs the registers.
Axi_clkgen generates the clock frequency required for the desired resolution (pixel clock), the frequency is software configurable.

Examples for different data width configurations

The ADV7511 can accept video data from as few as eight pins (either YCbCr 4:2:2 double data rate [DDR] or YCbCr 4:2:2 with 2x pixel clock) to as many as 36 pins (RGB 4:4:4 or YCbCr 4:4:4). In addition it can accept HSYNC, VSYNC and DE (Data Enable)

The axi_hdmi_tx core support the following video input connections:

  • 36 bits with HSYNC, VSYNC and DE
  • 24 bits with HSYNC, VSYNC and DE
  • 16 bits with HSYNC, VSYNC and DE
  • 16 bits with embedded SYNC

Software support

The core can be controlled by no-Os or Linux


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