Datastorm DAQ GHRD add display - ArrowElectronics/data-storm-daq GitHub Wiki

Add Video IP

This design uses the Analog Devices® AXI_HDMI_TX IP core to implement the HDMI interface to the display monitor.
Detailed information about the HDMI IP core can be found on the Datastorm-DAQ-GHRD-hdmi page.

The HDMI interface requires multiple IP cores from the IP Catalog

Add HDMI PLL IP

  • type pll in the IP Catalog search bar and find the PLL Intel FPGA IP,
  • Double click it to add it to the System Contents.
  • In the wizard, make the following settings:
    • In the General tab, insure the Reference Clock Frequency is set to 100.0 MHz,
    • Un-check the Enable locked output port,
    • Change the outclk0 Desired Frequency to 148.5 MHz,
    • Click Finish.
  • Rename it in the System Contents tab to hdmi_pll by right click the name -> Rename,
  • Under sys_hps, connect its refclk port to the h2f_user1_clock spine,
  • Under sys_hps, connect its reset port to the h2f_reset spine,

Add HDMI DMA IP

  • Type axi_dmac in the IP Catalog search bar to find it in the Analog Devices Library,
  • Double click it to add it to the System Contents,
  • In the wizard, make the following settings then click Finish:
    • Change the Source Type to Memory-Mapped AXI
    • Change the Destination Type to Streaming AXI
    • Check the Features boxes for Cyclic Transfer Support and 2D Transfer Support,
    • Check the AXI Stream interface common configuration box for AXI Stream interface has TLAST
    • Click Finish.
  • Rename it in the System Contents tab to hdmi_dmac_0 by right clicking the name -> Rename,
  • Under sys_hps, connect its s_axi_clock, m_src_axi_clock, and if_m_axis_aclk ports to the h2f_user1_clock port.
  • Under sys_clk, connect its s_axi_reset, and m_src_axi_reset ports to the h2f_reset spine.
  • Under sys_hps, connect its s_axi bus to the h2f_lw_axi_master port.
  • Under sys_hps, connect its interrupt_sender port to both the f2h_irq0 and f2h_irq1 ports.
  • Under sys_hps, connect is m_src_axi bus to the f2h_sdram0_data bus.

Add HDMI TX IP

  • Type axi_hdmi_tx in the IP Catalog search bar to find it in the Analog Devices Library,

  • Double-click it to add it to the System Contents, accept all default settings in the wizard, and Click Finish.

  • Under sys_hps, connect its s_axi_clock, and vdma_clock ports to the h2f_user1_clock port.

  • Under sys_clk, connect its s_axi_reset, and vdma_reset ports to the clk_reset spine.

  • Under hdmi_dmac_0, connect its vdma_if bus to the m_axis bus.

  • Under sys_hps, connect its s_axi bus to the h2f_lw_axi_master bus.

  • Under hdmi_pll, connect its hdmi_clock to the outclk0 port.

  • Double-click the Export column of the hdmi_if and name it hdmi_out.

Next - Adding Other Peripherals
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