Trenz Cyclone-V SoC Development Kit (TEI0022)

Analog Devices EVAL-ADRV9002NP/W1/PCBZ Development Board

The ADRV9002 Platform uses 2 boards. These are the Cyclone-V SoC Development Kit, and the EVAL-ADRV9002NP/W1/PCBZ (or EVAL-ADRV9002NP/W2/PCBZ) board which connect together via an FMC interface.

The Trenz Electronics TEI0022 SoC Development Kit is based on the Intel Cyclone V SoC FPGA. It features, 1GB DDR3 each for the HPS and FPGA, 32MB QSPI memory each for the HPS and FPGA, Ethernet, and Power. For details, visit the Trenz Electronics Technical Reference Manual Wiki page.

The major components of the Trenz Cyclone-V SoC Development Kit are identified by numbers:

Intel Cyclone-V SoC

• SX Processor:
  • Single or Dual ARM Cortex® A9 MPU
  • Up to 925 MHz max clock speed
  • 32KB L1 Program Cache (per core)
  • 32KB L1 Data Cache (per core)
  • 512 KB L2 Cache (shared)
  • 181 HPS I/O pins
  • 1 Hard Memory Controller (LPDDR2, DDR2, DDR3)
• FPGA Fabric:
  • Up to 110K Logic Elements (LE)
  • Up to 5.5Mb M10K Memory
  • Up to 621Kb MLAB Memory
  • Up To 112 Variable Precision DSP blocks
  • Up to 224 18x18 multipliers
  • Up to 288 User FPGA I/O pins
  • 1 Hard Memory Controller (LPDDR2, DDR2, DDR3)

FPGA DDR3
HPS DDR3
FMC LPC Connector
PMOD x4
microSD Card Connector
Ethernet PHY
RJ-45 Ethernet Connector
USB PHY
USB HUB
dual USB-A Connector
HDMI Transmitter
HDMI Connector
Intel MAX-10
micro-USB to UART Connector for HPS Console
USB to JTAG and UART FTDI Bridge
micro-USB to JTAG and UART Connector for FPGA
SMA Connector
Push Button
LED
4-bit DIP Switch
12 VDC Power Jack
Clock Generator
Programmable Clock Generator
QSPI for HPS
QSPI for FPGA
Temperature Sensor
EEPROM

The EVAL-ADRV9002 development board comes in 2 flavors, one is Low Band (EVAL-ADRV9002NP/W1/PCBZ) which supports a RF frequency range of 30MHz to 3GHz, and one High Band (EVAL-ADRV9002NP/W2/PCBZ) which supports a RF frequency range of 3GHz to 6GHz. Two power rails enter the board from the FMC connector, 12VDC and 3.3_AUX. The ADP5056 is used to generate 3 other rails; 1.8V, 1.3V, and 1.0V. Each of these rails has an analog and a digital version where each can have their voltages and current consumption monitored by an ADM1293 via I2C bus.

The reference clock can come from an on-board 38.4MHz TCXO, or via J501 SMA connector. These 2 clock sources go thought an RF switch (HMC849A). The switch select is controlled by a mechanical slide switch (S501). The selected clock is then distributed to the ADRV9002 and FPGA usingthe ADCLK944 clock fanout buffer.

A MultiChip Synchronization (MCS) signal source can be brought in via SMA J502 and distributed, by another ADCLK944, to the ADRV9002 and the FPGA..

Full descriptions of these products are available in their respective data sheets, which must be consulted when using the corresponding evaluation board.

ADRV9002 - RF Transceiver
ADP1762 - Low Noise CMOS LDO
ADM1293 - Digital Power Monitor with PMbus
EEPROM
38.4MHz TCXO
ADP5056 - Triple Buck Regulator Integrated Power Solution
LTC3621 - 17V Buck Regulator
ADCLK944 4 Output LVPECL Clock Fanout Buffer
HMC849A - High Isolation SPDT Switch, DC to 6GHz
AD8045 - Ultralow Distortion, high speed OpAmp
ADP1755 - 1.2A LDO
LPC FMC Connector
SMA - MCS Input
SMA - DEV_CLK Input
Clock Source Select slide switch
SMA - TX2 Output
SMA - Rx2A Input
SMA - LO2 Input
SMA - Rx2B Input
SMA - Rx1B Input
SMA - LO1 Input
SMA - Rx1A Input
SMA - Tx1 Output

The block diagram of the EVAL-ADRV9002NP/Wx/PCBZ board (below) shows the major components.

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