The Analog Device's AD7606B is an 8-channel SAR analog-to-digital converter (ADC), enabling synchronized sampling of AC and DC signals. (For detailed operation and specifications refer to the datasheet.)

The interface for the AD7606B digital host is the axi_ad7606b module in the Cyclone V FPGA. The block diagram is shown here:

This module receives 8 channels of conversion data from the AD7606B on the spi serial bus with 4 channel sdi or on the parallel bus DB. This data is synchronous to sclk in the serial interface or RD_N in the parallel interface and framed by busy signal negative edge. The busy signal acts as a trigger for data sampling in axi_ad7606b and is generated by ADC AD7606B on the assertion of the cnvst signal from FPGA, which acts as a start of conversion. The serial data from each channel is collected and presented in a 16-bit sign-extended parallel bus format. This is arranged as adc_data framed with adc_valid and adc_sync signals in order to be connected to any fifo based interface. In parallel mode, the data is also presented as 16-bit sign-extended for each channel as adc_data_chx, where x represents the channel number. This is framed with the adc_valid_pp signal for interfacing with the AD7606B pack module.

Name	Description
axi_ad7606b.v	Verilog source
axi_ad7606b_hw.tcl	Platform designer tcl file for ad7606B IP subsystem

Name	Description
ID	Setting ID to device module
IF_TYPE	Selects interface type for the ADC 0 - serial interface , 1 - parallel interface
NUM_OF_SDI	Number of sdi channel in ADC SPI bus for serial interface
NUM_OF_CHANNELS	Setting number of ADC data channels
ADC_TYPE	ADC type used in AD76xx family, 0 - for AD7606B
ADC_RESOLUTION	Size of ADC data per sample for each channel
DATA_WIDTH	Data size for Data bus within axi_ad7606B module

Name	Description
S_AXI_ACLK	AXI bus clk signal for AXI interface of axi_ad7606b
S_AXI_ARESETN	AXI bus active low reset signal for AXI interface of axi_ad7606b
S_AXI	slave AXI bus interface of axi_ad7606b
DB_i	Parallel ADC data in bus for parallel interface. ADC_RESOLUTION sets the number of parallel lines in this bus
DB_o	Parallel ADC data out bus for parallel interface. ADC_RESOLUTION sets the number of parallel lines in this bus
DB_t	Parallel bus Data flow direction selection. 1 connects DB_i to bidirectional parallel bus ,0 connects DB_o to bidirectional parallel bus
BUSY	Input signal from ADC to PFGA for Busy in conversion indication. data to be sample after falling edge of this signal
CNVST	Output signal from FPGA to ADC indicating start of conversion. In response to this ADC sends BUSY signal.
SCLK	Serial clock out from FPGA for SPI bus used in `serial interface1
CS_N	Active low chip select from FPGA for enabling ADC communication
SDO	Serial Data out from FPGA for SPI bus in serial interface
SDI	Serial Data in for FPGA for SPI bus in serial interface. NUM_OF_SDI parameter sets number of input serial data in channels
RD_N	Active Low read enable signal from FPGA to ADC used in parallel interface
WR_N	Active Low write enable signal from FPGA to ADC used in parallel interface;
ADC_DATA	ADC conversion DATA sampled from ADC in parallel format. ADC_RESOLUTION sets the number of parallel lines in this bus
ADC_VALID	Active high signal indicating valid ADC data on ADC_DATA bus for FIFO interface
ADC_SYNC	Active high syncing signal for FIFO interface
ADC_VALID_PP	Active high signal indicating valid ADC data on ADC_DATA bus for PACK module
ADC_DATA_CHx	ADC conversion DATA sampled from ADC in parallel format for all channels. Here x represents channel number and set by NUM_OF_CHANNELS parameter. ADC_RESOLUTION sets the number of parallel lines for each channel in this bus
IRQ	IRQ signal for processor from SPI engine integrated within axi_ad7606b module. (refer block diagram below)
SPI_CLK	Clock source for SPI engine integrated within axi_ad7606b module. (refer block diagram below)

• SPI Engine
• axi_ad7616_pif
• axi_ad7616_maxis2wrfifo
• axi_ad7616_control
• UP_AXI

The axi_ad7606b module is connected to the AXI bus interface as a slave via the UP_AXI module. This converts complex AXI bus signals to simpler read and write channels with separate data lines, request (driven by the master) and acknowledge (driven by slave) control signals. This interface is used for configuring register maps of different modules. This interface is connected to the axi_ad7616_control block which interfaces to the ADC. When the ADC interface type is selected as Serial, (IF_TYPE == 0) the SPI Engine block is also connected to the up_axi bus. The irq signal from SPI Engine serves as an interrupt source from axi_ad7606b ip to Cyclone V SoC.

axi_ad7616_control acts as a control block. It includes a set of control registers. One such register, UP_CONV, takes a value and feeds it to the internal counter, which when enabled, generates the cnvst signal to the ADC AD7606B block periodically for continuous data sampling. The value of the UP_CONV register needs to be adjusted with the clock used so as to match Tcon time of 1.25us of AD7606B. In response, the ADC AD7606B sends the busy signal which axi_ad7616_control receives and adjusts in the FPGA clock domain and then sends it as a trigger_s pulse. When IF_TYPE == 1, the control block enables the axi_ad7616_pif block and generates register read / write and ADC read commands for the parallel interface.

There are two types of interface available with AD7606B for integration, namely the serial interface & the parallel interface. Either of these can be selected through the parameter IF_TYPE which acts as a hardware switch for the interface. The adc_data and other respective signals are further selected and routed via MUX as shown in the above block diagram.

value	selection
IF_TYPE == 0	Serial Interface
IF_TYPE == 1	Parallel interface

In the AD7606B module, the SPI Bus is an available serial interface that is controlled by the SPI Engine module. It takes the spi command stream and data from the processor via up_axi and is executed in spi format to be able to communicate with the ADC AD7606B. It is used for SPI register reads and writes from the AD7606B. There is an offload engine which is used to execute ADC data reads automatically whenever an external trigger signal like trigger_s is asserted to its trigger input. The Data received is then bypassed from the main bus as offload_sdi_data and further interfaced with a valid and ready signal to axi_ad7616_maxis2wrfifo block. The AD7606B SPI block uses a four-input sdi channel. 16bit ADC data is collected over this channel (two channels on each sdi line) for each channel. For details refer to the datasheet. The axi_ad7616_maxis2wrfifo block converts 8-channel of 16bit offload_sdi_data to adc_data and arranges it sequentially in a 128-bit parallel format. In addition, it generates adc_sync and adc_valid signals to be able to interface with any FIFO logic. The adc_data_chx data and adc_valid_pp signals are generated by this block for interfacing with the PACK module (16-bit parallel data format for each ADC channel).

Note: For the parallel interface the SPI Engine module uses a modified version of SPI Engine Execution. This modification was necessary to get High ADC Data throughput of 800ksps for AD7606B and an sclk setting = 50Mhz. This modification is applicable for sclk = 50~60 Mhz.

The parallel interface for ADC AD7606B is controlled by the axi_ad7616_pif module which generates RD_N and WR_N signals which are the active low read and write command signals respectively. It receives/sends 16-bit parallel data over the DB bus to communicate with AD7606B. The trigger_s signal from the control block initiates an ADC data read stream from the FPGA. The 16-bits of data for each of the 8 channels are collected sequentially on the parallel bus (For details refer to datasheet) and converted to the 16-bit adc_data, adc_sync and adc_valid signals necessary to interface with the DMA fifo interface. The adc_data_chx data and adc_valid_pp signals are also generated by this block for interfacing with the PACK module. The formatting is 16-bit parallel data for each ADC channel.

Note: The AD7606B ADC driver works with an SPI device node, For the parallel interface there is no SPI interface used. So in order to make AD7606B ADC driver work a AXI SPI Engine block of SPI Engine module is added as a dummy.

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