AD7606B Platform FPGA Architecture SPI Engine Execution Module - ArrowElectronics/data-storm-daq GitHub Wiki

The SPI Engine Execution peripheral forms the heart of the SPI Engine framework. It is responsible for handling an SPI Engine control stream and translates it into low-level SPI bus transactions. NOTE: here SPI Engine Execution_1 is a modified version of the SPI Engine Execution HDL module specifically for the AD7606B. At SCLK > 40MHz, to ensure proper FPGA timing closure of the SDI data line, the ONE_BIT_SHIFT parameter was added. Setting ONE_BIT_SHIFT=0 causes the SPI Engine Execution to work in its original HDL flow, while ONE_BIT_SHIFT=1 ensures that the SDI logic captures data usingsclk instead of the trigger_rs signal. This also captures SD1 bit 0 live. This logic was added to ensure successful timing closure in the FPGA when sclk=50Mhz and the AD7606B is at full throughput of approximately 800ksps. HDL code details can be found at the link below.

Name	Description
spi_engine_execution_1.v	Verilog source for the peripheral.
spi_engine_execution_v1_0_hw.tcl	TCL script to generate Platform Designer IP

Name	Description	Default
NUM_CS	Number of chip-select signals for the SPI bus (min: 1, max: 8)	1
DEFAULT_SPI_CFG	Reset configuration value for the SPI Configuration Register	0
DEFAULT_CLK_DIV	Reset configuration value for the prescaler clock divider register	0
DATA_WIDTH	Data width of the parallel data stream. Will define the transaction's granularity. Supported values: 8/16/24/32	8
NUM_OF_SDI	Number of multiple SDI lines, (min: 1, max: 8)	1
SDI_DELAY	Internal delay for SDI data capture time closure, (min: 0, max: 3)	0
ONE_BIT_SHIFT	For getting one bit shifting for SDI data capture time closure required in some ADC for SCLK > 40Mhz	1

Name	Type	Description
clk	Clock	All other signals are synchronous to this clock.
resetn	Synchronous active-low reset	Resets the internal state machine of the core.
active	Output	Indicates whether the peripheral is currently active and processing commands.
ctrl	SPI Engine Control Interface slave	SPI Engine Control stream that contains commands and data for the execution module.
spi	SPI bus interface master	Low-level SPI bus interface that is controlled by peripheral.

The SPI Engine Execution module implements the physical access to the SPI bus. It implements a small but powerful programmable state machine that translates a SPI Engine command stream into low-level SPI bus access.

Communication with a command stream generator happens via the ctrl interface and the low-level SPI access is handled on the spi interface. The active signal is asserted as long as the peripheral is busy executing incoming commands.

Internally, the SPI Engine execution module consists of an instruction decoder that translates the incoming commands into an internal control signal, a multi-function counter and comparison unit that is responsible for handling the timing, and a shift register which holds the received and transmitted SPI data.

The module has an optional programmable pre-scaler register that can be used to divide the external clock to the counter and comparison unit.

SPI Engine

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