AD7606B Platform FPGA Architecture FIFO - ArrowElectronics/data-storm-daq GitHub Wiki

The axi_ad7616_maxis2wrfifo module receives 128-bit parallel 8channel adc_data of AD7606B with valid and sync signal on its m_axis_data along with m_axis_valid and m_axis_syncfrom SPI_Engine offload module and converts it into proper aligned FIFO write interface signal of 128-bit parallel fifo_wr_data along with its fifo_wr_en and fifo_wr_sync signal for interfacing with DMA fifo source interface

Name	Description
axi_ad7616_maxis2wrfifo.v	Verilog source

Name	Description
DATA_WIDTH	Setting data width of data channel
ADC_TYPE	selecting ADC type for data allingment, 1 selects ADC AD7606B

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