The AD7606B digital host consists of DSP (digital signal processor), or an FPGA (Field Programmable Gate Array). In this case we use the Intel Cyclone V SoC FPGA with a dual core ARM Cortex A9 hard processor system (HPS) with the embedded Analog Devices axi_ad7616_06b IP block as depicted here.

The Intel Cyclone V SoC FPGA serves as the digital host for the AD7606B ADCs. It also implements various interfaces and modules for configuration, control, status, dma, as well as conversion data processing and host processing. Additionally, there are external data/control and video peripheral interfaces implemented in the FPGA for use on the DataStorm DAQ.

The AD7606B can use either a serial or parallel interface for configuration or data acquisition. The FPGA receives the ADCs conversion data over the db parallel bus (if AD7606B parallel interface is used ) or SPI with 4 SDI channel (if AD7606B serial interface is used ) and provides configuration and control over RD and WR for parallel interface and SPI bus for the serial interface. The interfaces implemented are described below. For details, consult the AD7606B datasheet and its operation on the EVAL-AD7606B-FMCZ dev board.

• axi_ad7606b
• AD7606B PACK
• AD7606B DMA
• AD7606B ADC

The toplevel ports for the fpga are as follows:

Name	Direction	Description
sys_clk	input	main clock
ddr3_a[15:0]	output	HPS DDR3 Address bus
ddr3_ba[2:0]	output	HPS DDR3 Bank Address
ddr3_reset_n	output	HPS DDR3 acvite low Reset
ddr3_ck_p	output	HPS DDR3 Differential clock positive rail
ddr3_ck_n	output	HPS DDR3 Differential clock negative rail
ddr3_cke	output	HPS DDR3 clock enable
ddr3_cs_n	output	HPS DDR3 active-low chip select
ddr3_ras_n	output	HPS DDR3 active-low row address strobe
ddr3_cas_n	output	HPS DDR3 active-low column address strobe
ddr3_we_n	output	HPS DDR3 active-low write enable
ddr3_dq[31:0]	inout	HPS DDR3 32-bit bidirectional data bus
ddr3_dqs_p[3:0]	inout	HPS DDR3 4-bit bidir differential data strobe positive rail
ddr3_dqs_n[3:0]	inout	HPS DDR3 4-bit bidir differential data strobe negative rail
ddr3_dm[3:0]	inout	HPS DDR3 4-bit bidir data mask
ddr3_odt	output	HPS DDR3 on-die termination
ddr3_rzq	output	HPS DDR3 output drive calibration (to RZQ resistor)
eth1_tx_clk	output	HPS ethernet mac transmit interface clock
eth1_tx_ctl	output	HPS ethernet mac transmit interface control
eth1_tx_d[3:0]	output	HPS ethernet mac transmit interface 4-bit data bus
eth1_rx_clk	input	HPS ethernet mac receive interface clock
eth1_rx_ctl	input	HPS ethernet mac receive interface control
eth1_rx_d[3:0]	input	HPS ethernet mac receive interface 4-bit data bus
eth1_mdc	output	HPS ethernet mac management data i/o interface clock
eth1_mdio	inout	HPS ethernet mac management data input/output
link_st	inout	HPS ethernet mac link state
rx_er	inout	HPS ethernet mac receive error
phy_int	inout	HPS ethernet PHY interrupt
eth_rst	inout	HPS ethernet reset
phy_led1	inout	HPS ethernet PHY led 1
qspi_ss0	output	HPS Quad SPI chip select 0
qspi_clk	output	HPS Quad SPI clock out
qspi_io[3:0]	inout	HPS Quad SPI data 3 to 0
sdio_clk	output	HPS SDIO Clock
sdio_cmd	inout	HPS SDIO command
sdio_d[3:0]	inout	HPS SDIO bidir data
usb1_clk	input	HPS USB interface clock
usb1_stp	output	HPS USB interface STOP signal
usb1_dir	input	HPS USB interface Direction
usb1_nxt	input	HPS USB interface Next
usb1_d[3:0]	inout	HPS USB interface 8-bit bidir data
usb1_rst	inout	HPS USB interface reset
uart0_rx	input	HPS UART0 RX data
uart0_tx	output	HPS UART0 TX data
hps_scl	inout	HPS I2C interface serial clock
hps_sda	inout	HPS I2C interface serial data
hdmi_clk	output	HDMI Clock
hdmi_de	output	HDMI Data enable
hdmi_hsync	output	HDMI Horizontal Sync
hdmi_vsync	output	HDMI Vertical Sync
hdmi_data[23:0]	output	HDMI Data
hdmi_spdif	output	HDMI Sony/Philips Digital Interface
hdmi_spdifout	input	HDMI Sony/Philips Digital Interface out
hmdi_int	input	HMDI int
ct_hpd	output
ls_oe	output
cec_clk	output	Consumer Electronics Control Clk
fmc_scl	inout	FMC I2C clock
fcm sda	inout	FMC I2C data
ad7606b_busy	input	ADC busy in data conversion signal from AD7606B ADC
ad7606b_cnvst	output	ADC start of conversion signal for AD7606B ADC
ad7606b_csn	output	Active-low SPI chip select
ad7606b_sclk	output	SPI Clock to AD7606B ADC
ad7606b_sdo	output	SPI data out to AD7606B ADC
ad7606b_sdi[3:0]	input	SPI data in from AD7606B ADC
ad7606b_wrn	output	Active low write signal for parallel mode in AD7606B ADC
ad7606b_rdn	output	Active low read signal for parallel mode in AD7606B ADC
ad7606b_db[15:0]	input	Parallel interface data line in AD7606B ADC
ad7606b_os0	output	Oversampling selection pin0 in AD7606B ADC
ad7606b_os1	output	Oversampling selection pin1 in AD7606B ADC
ad7606b_os2	output	Oversampling selection pin2 in AD7606B ADC
ad7606b_reset	output	Active-low reset for AD7606B ADC
ad7606b_frstdata	input	Indication for channel 1 data in transfer in AD7606B ADC
ad7606b_range	output	Voltage range selection in AD7606B ADC
ad7606b_refsel	output	Internal/external reference selection for AD7606B
ad7606b_serpar	output	Serial/parallel interface selection in AD7606B ADC
ad7606b_stby	output	Power saving by standby in AD7606B ADC
fmc_pg_c2m	inout
fmc_prsnt_m2c	inout
cpu_gpio_0	inout
cpu_gpio_1	inout
led_hps_1	inout
led_hps_2	inout
therm_n	inout
alert_n	inout
user_btn_hps	inout
status	inout
as_rst	inout
qspi_rst	inout

Note: Hdl design for AD7606B is based on 4SDI line for all channels to receive at throughput 800Ksps in Serial interface.

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