Introduction

This section describes how to download the HDL design from the github repository. The designs can be built by using make in a shell. The following steps describe how to do this which conclude by calling a makefile with the make command.

This will build the Platform Designer™ (formerly called QSys™) and Quartus® projects, and then generate and compile them. This approach guarantees quality of results for anyone initially working with these designs.

Building A Cloned HDL Project

1 - Create a working directory

Create a directory where all the project repositories can be cloned from github.

• Open a shell in the VM player (Ctrl+Alt+T)

    $ cd ~
    $ mkdir ad7606b
  

2 - Launch a Nios II Command Shell

    $ ~/intelFPGA_lite/20.1/nios2eds/nios2_command_shell.sh

2 - Clone the HDL repository

• navigate to the directory where the project will be stored

    $ cd ad7606b
    $ git clone https://github.com/ArrowElectronics/hdl.git 
  

• then do the following to update the files in the working tree...

    $ cd hdl  
    $ git checkout R20.1_TE_DSD_1.0
  

3 - Execute the build

    $ cd projects/ad7606b_fmc/tei0022/   
    $ make build  

• Enter option 0 to build for Serial Mode operation.

• Enter option 1 to build for Parallel Mode operation.

• Warning: Any input other than 0 and 1 will throw an error.

NOTE: The serial and parallel options are a 'hardware' switch. Please rebuild the design if you wish to change the interface.

The build can take a significant period of time to complete. Open and regularly refresh the ad7606b_fmc_tei0022_quartus.log file in a text editor to monitor progress. This is located in the hdl/projects/ad7606b_fmc/tei0022 subdirectory.

---

Next - Build uboot

Return to Build the Example Design
Return to AD7606B Platform User Guide