The ad738x_dma accepts the source interface data width in power of 2 i.e 8/16/32/64/128/256 bit. The offload_sdi_data from SPI Engine Offload Module for each channel is either of 18/16/14/12 bit data width. Upscale Converter_2 prepends this offload_sdi_data with zero padding to match the dma source interface data width. Here in ad738x, any ADC max resolution >16bit is upscaled to 32bit whereas resolution =<16bit is upscaled to 16bit for each channel. There are a total of two channels for AD738x family.

This module receives 2 channels of conversion data from the AD738x on the offload_sdi_data bus from SPI Engine Offload Module on the s_axis bus with its ready and valid signal. This data is then upscaled to the respective dma source data width and forwarded to dma on m_axis. The AD738x family ADC has a resolution boost feature which increases ADC bit resolution by 2. This increase in 2 bits is handled by upscale_converter_2 with the help of the bit_2_shift signal. This signal is controlled through a GPIO pin.

Name	Description
util_axis_upscale_2.v	Verilog source
util_axis_upscale_v2_0_hw.tcl	Platform designer tcl file for upscale converter

Name	Description
NUM_OF_CHANNELS	Setting number of (ADC) data channels
DATA_WIDTH	Size of data bus from source interface
UDATA_WIDTH	Size of data bus for destination interface

Name	Description
clk	Clk signal for upscale_converter_2
resetn	Active low reset signal for upscale_converter_2
s_axis_data	Source interface data bus, parameter DATA_WIDTH & NUM_OF_CHANNELS controls the bus width
s_axis_valid	Data valid signal from Source interface
s_axis_ready	Ready signal to Source interface
m_axis_data	Destination interface data bus, parameter UDATA_WIDTH & NUM_OF_CHANNELS controls the bus width
m_axis_valid	Data valid signal for Destination interface
m_axis_ready	Ready signal from Destination interface
bit_2_shift	Setting shift signal High adjust 2bit lower resolution data on current Source interface data bus width

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