AD738x Platform FPGA Architecture - ArrowElectronics/data-storm-daq GitHub Wiki

AD738x Platform FPGA Architecture

The kit is configured to allow the user to receive data in the Cyclone® V SoC from the AD738x's ADC using a serial SPI interface over the FMC LPC connector.

Note: Hdl design for AD738x is based on 2wire mode(SDIx2) for max adc data throughput.

SPI Engine

SPI Engine is a highly flexible and powerful SPI controller framework. It consists of multiple sub-modules which communicate over well-defined interfaces. This allows a high degree of flexibility and re-usability, while at the same time staying highly customizable and easily extensible.



The core component of the SPI Engine framework is a lean but powerful fully-programmable execution module, which implements the SPI bus-control logic. The SPI Engine execution module is controlled by a command stream which is generated by a separate module. Different command stream master modules are available and can be used depending on the system requirements. For example, a software-controlled memory-mapped command stream offers high flexibility, while an offload core, which executes a pre-programmed command stream when triggered by an external event (in this case a (cnv)pulse from pulse_generator), allows for very low latency response times. By using a SPI Engine interconnect it is possible to connect multiple command stream master modules to a SPI Engine execution module.

Sub-modules

from right to left

Software

Additional Documents




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