The AD4630-24 is a two-channel, simultaneous sampling, Easy Drive, 2 MSPS successive approximation register (SAR) analog-to-digital converter (ADC). With a guaranteed maximum ±0.9 ppm INL and no missing codes at 24 bits

The interface for the AD463x digital host is the axi_ad463x_if module in the Cyclone V FPGA. The block diagram is shown here:

This module receives two channels of conversion data from the AD463x at a time on the spi serial on bus spi X 8 . This data is synchronous to spi_clk, echo_clk & master_clk(depending on mode selected in 0x20 register in AD463x) in the serial interface and is framed by the rx_cnv signal positive edge. The rx_cnv signal also acts as a trigger for data sampling internally in axi_ad463x_if. The rx_cnv signal is generated by the axi_ad463x_if through an internal pulse counter logic which acts as a start of conversion for AD463x. For more details refer datasheet.

Name	Description
axi_ad463x_if.v	Verilog source
axi_ad463x_if_hw.tcl	Platform designer tcl file for ad463x IP subsystem

Name	Description
ID	Setting ID to device module
NUM_OF_SDI	Number of sdi channel in ADC SPI bus for serial interface
NUM_OF_CHANNELS	Setting number of ADC data channels
ADC_RESOLUTION	Size of ADC data per sample for each channel
DATA_BUS	Data size for Data bus within axi_ad463x_if module

Name	Description
S_AXI_ACLK	AXI bus clk signal for AXI interface of axi_ad463x
S_AXI_ARESETN	AXI bus active low reset signal for AXI interface of axi_ad463x
S_AXI	slave AXI bus interface of axi_ad463x
rx_cnv	Output signal from FPGA to ADC indicating start of conversion
spi_clk	Serial clock out from FPGA for SPI bus
rx_cs_n	Active low chip select from FPGA for enabling ADC communication
rx_sdo	Serial Data out from FPGA for SPI
rx_sdi	Serial Data in for FPGA for SPI bus . NUM_OF_SDI parameter sets number of input serial data in channels
rx_echo	echo clock in from AD463x for FPGA for SPI bus
rx_busy	multiplexed busy/ master clock in from AD463x for FPGA for SPI bus
adc_data	ADC conversion DATA packed. ADC_RESOLUTION and NUM_OF_CHANNELS sets the width in this bus
adc_valid	Active high signal indicating valid ADC data on ADC_DATA bus for FIFO interface on dma
adc_ready	Active high syncing signal for FIFO interface on dma
IRQ	IRQ signal for processor from SPI engine integrated within axi_ad463x_if module. (refer block diagram below)
SPI_CLK	Clock source for SPI engine integrated within axi_ad463x_if module. (refer block diagram below)

Address		Name	Description
DWORD	BYTE
0x0404	0x0101	UP_CNV_RATE	Sets the rate of cnv pulse
0x0408	0x0102	CNV_PULSE_WIDTH	Sets the pulse width of cnv pulse
0x040C	0x0103	{14'b0, up_cnv_en, up_resetn}	to enable internal pulse counter and reset mode
0x041C	0x0104	UP_SCRATCH	scratch pad register
0x0410	0x0105	{8'b0,num_of_lanes,clk_md,ddr_sdr_n,test}	to enable ddr and sdr modes and select num_of_lanes and clock configuration
0x0410	0x0106	UP_VCOM[0]	buffer VCOM voltage reading from AD463x channel 1
0x0410	0x0107	UP_VCOM[1]	buffer VCOM voltage reading from AD463x channel 2

• SPI Engine
• UP_AXI
• Data_Capture

The data and control stream from the processor is received through the s-axi interface which is then simplified into a simple microprocessor bus through up_axi module. The microprocessor bus is shared by both the spi_engine module and the internal configuration registers of axi_ad463x_if module. A internal pulse counter generates a rx_cnv periodically as set by the up_cnv register. The rx_cnv pulse width is adjusted by the CNV_PULSE_WIDTH register. This rx_cnv pulse acts as a trigger signal for the spi_engine module.

below are the tested and supported clock mode, number of lanes & data mode for data capturing in axi_ad463x_if module.

	1 Lane per channel	2 Lane per channel	4 Lane per channel
SPI Mode	SDR	SDR	SDR (default)
Echo Clock Mode	SDR & DDR	SDR & DDR	SDR & DDR
Master Clock Mode	SDR	SDR	SDR

The ADC data adc_data from data_rearrange block is in format of 64bit (32x2) data width. The data width is set by NUM_OF_CHANNEL and ADC_RESOLUTION parameters. With data adc_valid signal is generated which act as valid signal for FIFO interface on dma module. data_rearrange arrange 8bit stream of adc data in 32x2 bit as per num_of_lanes selected which depend on Lanes used in AD463x for data.

In AD463x SPI Bus is available which is controlled by SPI Engine module. It take spi command stream and data from processor and executed in spi format to able to communicate to and fro with ADC AD463x. It is used for SPI register read and write from AD463x. There is offload engine which is used to execute ADC data read automatically whenever external trigger signal like trigger_s is given to its trigger input. The Data received is then bypassed from main bus as offload_sdi_data and further interface with a valid and ready . 32bit ADC data is collected in 8bit stream manner from x8 sdi spi lanes with 24-bit differential data + 8-bit common mode data for each channel. The data is received from AD463x in either of 1,2 & 4 sdi lanes. offload sdi data and valid signal is given to mux as data_in_s and data_valid_s and passed through as data_in and data_valid when spi mode clk_md=2'b00 is used. For details refer datasheet.

In AD463x SPI Bus can also be controlled by sclk generated from AD463x either from echo_clk or master clk. Based on this clock data is sampled in data_capture block either in sdr or ddr fashion based on configuration sdr_ddr_n=0 selected in AD463x. The data is received from AD463x in either of 1,2 & 4 sdi lanes. The Data received is then forwarded to mux as data_in_e and data_valid_e and passed through as data_in and data_valid when echo mode clk_md=2'b10 or 2'b01 is used. For details refer datasheet.

---

Return to AD463x Platform FPGA Architecture

Information on this site was obtained from