The sub interface for the axi_ad463x_if module is ad463x_data_capture module in the Cyclone V FPGA. The block diagram is shown here:

This module receives conversion data from the AD463x at a time on the spi bus on sdi x8 lanes . This data is synchronous to echo_clk/ master_clk in the serial interface . The csn signal also acts as a reset and trigger for clock pulse counter internally in ad463x_data_capture.

Name	Description
axi_ad463x_data_capture.v	Verilog source

Name	Description
NUM_OF_SDI	Number of sdi channel in ADC SPI bus for serial interface
DATA_BUS	Data size for Data bus within ad463x_data_capture module

Name	Description
csn	Active low chip select signal for spi bus
sdi	Serial Data in for FPGA for SPI bus . NUM_OF_SDI parameter sets number of input serial data in channels
echo_clk	echo clock out from FPGA for SPI bus
spi_clk	System clock for data capture block for CDC
data_in_e	Parallel Data out from data capture block from SPI
data_valid_e	Parallel Data valid signal from data capture block
NUM_OF_LANES	Number of lanes configuration to be used for data valid signal generation
ECHO_EN	enable signal for data capture logic
DDR_EN	signal to select between sdr and ddr conversion logic in data capture

The data from AD463x is received through the sdi x8 lanes of spi bus synchronous to csn and echo_clk/rx_busy signal. Serial data is captured and converted parallel by independent sdr and ddr conversion block. These block are enable by ddr_en signals ddr_en=0 for ddr and ddr_en=1 for sdr conversion and data is parallel out in stream of 8bit as data_ddr and data_sdr respectively. Mux then selects among this data and output as data_in_e. Valid generator generates a data valid signal with help of clock pulse counter logic and output as data_valid_e after applying CDC technique referencing spi_clk.

below are the tested and supported clock mode, number of lanes & data mode for data capturing in ad463x_data_capture module.

	1 Lane per channel	2 Lane per channel	4 Lane per channel
Echo Clock Mode	SDR & DDR	SDR & DDR	SDR & DDR
Master Clock Mode	SDR	SDR	SDR

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