examine the live system - ArrowElectronics/arrow-soc-workshops GitHub Wiki
The reader has now built a Linux distribution tailored to the custom soc board. It is useful to explore the booted Linux system and examine some peripherals in the FPGA mapped to to Cortex-A9 processor.
Recall in the Building the Golden Hardware Reference Design (GHRD) section of the workshop that the FPGA peripherals to be added were listed with their respective address offsets within the FPGA.
The memory map of system peripherals in the FPGA portion of the SoC as viewed by the HPS (Cortex-A9) processor, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is as follows:
| Periheral | Platform Designer Address Offset | HPS Address | Size (bytes) | Attribute |
|---|---|---|---|---|
| sys_id | 0x1_0000 | 0xff21_0000 | 8 | Unique system ID |
| led_pio | 0x1_0040 | 0xff21_0040 | 8 | LED output display |
| dipsw_pio | 0x1_0080 | 0xff21_0080 | 8 | Push button input |
| button_pio | 0x1_00c0 | 0xff21_00c0 | 8 | DIP switch input |
| jtag_uart | 0x2_0000 | 0xff22_0000 | 8 | JTAG UART console |
The Lightweight HPS-to-FPGA bridge resides in the HPS memory map at 0xff20_0000. The FPGA peripherals addresses are added as an offset to this base address when viewed from the HPS portion of the device.
The devicetree for my-custom-soc-board was built using the methodology described in this section on Rocketboards. A few different approaches are discussed and this Linux build employed the Main system device tree integration method.
The devicetree source is hierarchical and uses a number of files. The custom soc board devicetree uses the following source files of interest.
| File | Description |
|---|---|
| socfpga_cyclone5_my_custom_soc_board.dts | custom, board specific, top level. enables selected HPS peripherals |
| socfpga_cylone5.dtsi | basic system setup for linux |
| socfpga.dtsi | defines all HPS peripherals |
| my_custom_soc_board_fpga.dtsi | defines all custom FPGA peripherals. declares fpga_leds |
| my_custom_soc_board_ghrd.h | FPGA peripheral header definition file |
At boot time the devicetree is loaded into memory by the bootloader and then parsed by the Linux kernel during boot. It is useful to examine the kernel to view the devicetree in a live system.
Login to the Linux system. Use 'root' at the login prompt.
List the the devicetree peripherals in the FPGA
$ ls /proc/device-tree/soc/base-fpga-region/
The peripherals declared in the my_custom_soc_board_fpga.dtsi devicetree include file are present. The leds that were declared are also present. The associated LED Linux driver is installed and each individual LED is present in the Linux system as an addressable device.
$ ls /sys/class/leds
Examine led0 features
$ ls /sys/class/leds/fpga_led0
DE10-Nano
DataStorm Daq
SoCKit
The compatible = "gpio-leds" statement in the devicetree on line 129 directs Linux to load the appropriate driver at boot time.
Since the fpga_ledx are Linux devices their current state can be modified as such.
The brightness property is provided and implemented by the driver.
A User space application can access the FPGA LEDs by addressing them using the syntax below.
( x is 0,1 for the DataStorm DAQ and the DE10-nano, and 0,1,2,3 for the SoCKit)
Turn the LED (fpga_led0) on
$ echo 1 > /sys/class/leds/fpga_led0/brightness
Turn the LED (fpga_led0) off
$ echo 0 > /sys/class/leds/fpga_led0/brightness
Return to - Build the Custom image
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