1. Overview
2. Reference Material
3. Program the FPGA
4. Start System Console
5. Controlling LEDs
6. Reading Push Button State
7. Sending Characters Using JTAG UART
8. Exercising Onchip RAM

System Console is an FPGA system debugging tool that is part of the Quartus Prime package.

This page demonstrates how to use the System Console to control the development board peripherals:

• Turn LEDs on and off
• Read pushbutton values
• Send characters to console through JTAG UART connection
• Read and write to the on-chip memory

Note that all the interaction happens between FPGA and System Console running on host PC. There is no software running on HPS.

For more information about System Console, refer to

• Analyzing and Debugging Designs with the System Console.
• System Console Whitepaper

1. Open Quartus® 20.1

2. Open the Programmer. Tools --> Programmer

3. Program the FPGA. Processing --> Start

1. If the project is not already open, In Quartus Prime, go to File -> Open Project and select the file ~/datastormdaq_ghrd/datastormdaq_ghrd_top.qpf

2. In Quartus Prime, open the System Console window by going to Tools --> System Debugging Tools --> System Console

3. Run the GHRD script by typing source ghrd_sc_script.tcl in the Tcl Console

The Development Kit has 2 LEDs that are connected to the FPGA. They are marked as "FPGA LED 1" and "FPGA LED 2". The LEDs are turned OFF by default.

1. Use the following command to turn all LEDs off:

led_off

1. Turn on FPGA LED 1 by typing the following command:

led_on 0x1

1. Turn on FPGA LED 2 by typing the following command:

led_on 0x2

6. Turn both LEDs on by typing the following command

led_on 0x3

The Development Kit has one push button that is connected to the FPGA. It is marked as USER BTN.

1. Type the following command to clear the parallel I/O (PIO) data register:

button_data_read_clear

2. Type the following command to enable interrupts from push button USER BTN:

button_intr_enable 0x1

3. Type the following command to start the interrupt monitoring in System Console:

irq_monitor_on

System Console will read the push button interrupt status every five seconds and display it on the console. It will initially show the button as not pressed.

4. Press button USER BTN on the development board. The irq monitor will indicate that the button is pressed until a button_data_read_clear will be run to clear the status.

5. Type the following command to turn off interrupt monitoring:

irq_monitor_off

The GHRD contains a JTAG UART soft IP core, that can be used to transfer data between FPGA and the host PC. On the host PC, the data is handled by the nios2-terminal application.

1. Start the Nios II Command shell. Open a shell and at the prompt type

    $ ~/intelFPGA_lite/20.1/nios2eds/nios2_command_shell.sh
   

2. Start the nios2-terminal application from a NIOS II command shell:

    $ nios2-terminal
   

3. In System Console, type the following commands to send characters to the host PC:

juart_data_write 0x48
juart_data_write 0x49

4. The NIOS Console will display the two characters that were sent, spelling the word "HI":

The GHRD contains an FPGA Onchip memory soft IP core. The System Console TCL script includes a simple memory test routine that writes some values to random memory locations and reads them back to verify they are correct.

In order to run the memory test for 4 locations, type the following command in the System Console:

mem_rand_test 4

Next - Building a Custom Linux BSP for SoC FPGA Systems Using the Yocto Project

Return to - Creating top level design

Return to - Designing with Custom SoC FPGA for DataStorm DAQ