Scratch Pad Page - ArrowElectronics/arrow-soc-workshops GitHub Wiki

• Select the Output Clocks sub-tab and change the following selections from their defaults:
  • In the Main PLL Output Clocks section, change the Configuration/HPS-to-FPGA user 0 clock frequency to 123.333333 MHz
  • In the Peripheral PLL Output Clocks section, change the QSPI clock frequency to 370.0 MHz

• In the PHY Settings sub-tab, set:
  • Memory clock frequency to 400.0 MHz
  • PLL reference clock frequency to 25MHz

• Select the Memory Parameters sub-tab and set the following:

  Memory device speed grade	800.0 MHz
  Total interface width	32 (which will automatically update the Number of DQS groups to 4)
  Row address width	15
  Column address width	10
  Memory CAS latency setting	5
  ODT Rtt nominal value	RZQ/6

• Select the Memory Timing sub-tab and set the values as shown in the figure below:

• Select the Board Settings sub-tab.
  • In the Board Skews section change the setting to match the figure below:

• Click Finish.

In the System Contents tab do the following:

• Double-click in the hps_io row Export column and call it hps_0_hps_io,
• Double-click in the h2f_reset row Export column and call it hps_0_h2f_reset,
• Make the following connections as show in the diagram below:

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