Getting Started with the SoCKit board - ArrowElectronics/arrow-soc-workshops GitHub Wiki

Overview

The Intel PSG SoC combines a Hard Processing System (HPS) and an FPGA on a single device. The HPS has dual core ARM Cortex-A9 Microprocessor Unit (MPU) and a host of peripherals such as DDR3 controllers, Ethernet MACs, SPI controllers, and many more.

The FPGA portion of the device is tightly coupled through high performance bridges to the HPS. The designer can add peripherals they create or third-party IP to the FPGA and map it into the HPS. Thus, you have a flexible and very powerful solution.

The HPS is configured using Platform Designer, Intel PSG's SoC/FPGA IP integration tool. Configuration includes selecting DDR memory, determining clock frequencies, and selecting which HPS peripherals your design will use.

Platform Designer is also used to define the HPS peripheral pin outs; Quartus is used to define the FPGA peripheral pin outs. These two Intel PSG FPGA development tools generate the files needed for the transfer of design information from the hardware to the software domain.

Acquire the SocKit

If you don't already have a SocKit, ask for a loaner from your local Arrow FAE

Get the Cyclone V SoCKit ready for the Labs

Connect cables to the connectors shown in the diagram below. All cables are provided in your SoCKit.

  • Connect the micro or mini (Rev E) USB cable to the USB host connector on your laptop and to the USB Blaster II connector on the SoCKit.
  • Connect the Power Supply to the Power connector on the SoCKit. Do not power on the board at this time.

There are a few jumpers that require configuring before proceeding with the labs.

  • BOOTSEL[2..0] jumpers. These should be configured as "100" to select boot from SD card 3.3V
  • CLKSEL[1..0] jumpers. These should be configured as "00" for the slowest HPS peripheral clock speed option.

Ensure that the jumpers are configured as indicated below.

Modify the default MSEL bit settings. The board needs to be set to configure in the FPPx32, fast, compressed mode. This will allow u-boot to configure the FPGA.

  • SW6 is located on the bottom side of the SoCKit.
  • Please change MSEL[0:4] to 01010.

Verify that the JTAG chain is correctly configured. The JTAG chain switch is located to the right of the green audio connector.

  • HSMC_EN should be disabled (left position) and the HPS_EN should be enabled (right position).

Connect the USB Blaster II as a device to the VM

  • Turn your SoCKit on by pressing the red power button next to the power connector.

  • Connect the Blaster to the Virtual Machine. From within the VM press

    Player --> Removable Devices --> Altera CV SoCKit --> Connect (Disconnect from Host)

  • Open a shell (Ctrl + Alt + T)

    $ ~/intelFPGA_lite/20.1/nios2eds/nios2_command_shell.sh 

$ jtagconfig

  • Type jtagconfig at the prompt and press enter.

  • If the jtagconfig command fails (“No JTAG hardware available”message), then the driver is not installed.

Next: Golden Hardware Reference Design (GHRD)
Back to: Custom SoC FPGA Workshop