Getting Started with the DE10 Nano board - ArrowElectronics/arrow-soc-workshops GitHub Wiki

Overview

The Intel PSG FPGA SoC combines a Hard Processing System (HPS) and an FPGA on a single device. The HPS has dual core ARM Cortex-A9 Microprocessor Unit (MPU) and a host of peripherals such as DDR3 controllers, Ethernet MACs, SPI controllers, and many more.

The FPGA portion of the device is tightly coupled through high performance bridges to the HPS. The designer can add peripherals they create or third-party IP to the FPGA and map it into the HPS. Thus, you have a flexible and very powerful solution.

The HPS is configured using Platform Designer, Intel PSG's SoC/FPGA IP integration tool. Configuration includes selecting DDR memory, determining clock frequencies, and selecting which HPS peripherals your design will use.

Platform Designer is also used to define the HPS peripheral pin outs; Quartus is used to define the FPGA peripheral pin outs. These two Intel PSG FPGA development tools generate the files needed for the transfer of design information from the hardware to the software domain.

Acquire the DE10 Nano

If you don't already have a DE10-Nano, it can be purchased from Arrow here: Terasic's DE10-Nano

Get the Cyclone V DE10-Nano ready for the Labs

Connect cables to the connectors shown in the diagram below. All cables are provided with your DE10-Nano.

  • Connect the micro USB cable to the USB host connector on your laptop and to the USB Blaster II (USB Mini-B) connector on the DE10-Nano.
  • Connect the Power Supply to the Power connector on the DE10-Nano. Do not power on the board at this time.

Before proceeding to the labs

  • Verify the FPGA Configuration Mode switches [5:0] are set to 01010 to boot the DE10-Nano board from the microSD card
  • Ensure the microSD card included in the kit is properly inserted

Ensure that the jumpers are configured as indicated below.

Connect the USB Blaster as a device to the VM

  • Turn your DE10-Nano board on by plugging the power adapter into an AC outlet.

  • Connect the Blaster to the Virtual Machine. From within the VM press

    Player --> Removable Devices --> Altera DE-SoC --> Connect (Disconnect from Host)

  • Open a shell (Ctrl + Alt + t)

    $ ~/intelFPGA_lite/20.1/nios2eds/nios2_command_shell.sh 

$ ~/intelFPGA_lite/20.1/quartus/bin/jtagconfig

  • Type jtagconfig at the prompt and press enter.

  • If the jtagconfig command fails (“No JTAG hardware available” message), then the driver is not installed.

    • Verify that you are connected to the USB Mini-B port located next to the HDMI-TX connector
    • IT may bump your board off of the VM and ask where you want to connect again when you issue the jtagconfig command. If so, connect to VM again, then re-issue the jtagconfig command.

Next - Terasic-DE10-Nano Golden Hardware Reference Design (GHRD)
Back to - Custom SoC FPGA Workshop with the Terasic DE10-Nano