Creating top level design - ArrowElectronics/arrow-soc-workshops GitHub Wiki
Top-Level design
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In Quartus Prime, Add the additional required files to the project.
Click Project -> Add/Remove Files in Project...
- Navigate to the project folder and add the following files.
File | Description |
---|---|
sockit_ghrd/synthesis/sockit_ghrd.qip | Platform Designer IP reference file |
ip/edge_detect/altera_edge_detector.v | edge detect verilog source file |
- Click OK in the Settings - system_top window.
Add assignments
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Perform the Analysis & Synthesis step to be able to add pin assignments,
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Open a Tcl Console in Quartus Prime by selecting
View -> Utility Windows -> Tcl Console
,- At the tcl prompt, type
$ cd ~/socfpga-workshop/socfpga_hw_workshop/sockit_ghrd
$ source sockit_ghrd_assign.tcl
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This will assign all pins for the project. There are a few hundred so this will take a few minutes to complete.
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Finish compiling the project by pressing the Start Compilation symbol .
Convert the FPGA image file to the Raw Binary Format (RBF)
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Open a Nios II Embedded Command Shell
$ ~/intelFPGA_lite/20.1/nios2eds/nios2_command_shell.sh
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Navigate to the FPGA image folder
$ cd ~/socfpga-workshop/socfpga_hw_workshop/sockit_ghrd/output_files
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Convert the FPGA image file to the RBF format
$ quartus_cpf -c -o bitstream_compression=on sockit_ghrd_top.sof soc_system.rbf
Next - Validating the GHRD with System Console
Back to - Adding other Peripherals
Back to GHRD top