Creating Processor System - ArrowElectronics/arrow-soc-workshops GitHub Wiki
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Open Platform Designer from Quartus Prime via one of the two methods below:
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Tools -> Platform Designer
menu, or - Click on its icon
in the tool bar. A blank project is created with a default name of unsaved.qsys.
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Do a
File -> Save As …
to give it the name sockit_ghrd.qsys. -
When Saving is done, click Close.

Either type HPS
in the IP Catalog search bar or, expand the Processors and Peripherals -> Hard Processor Systems
and double-click Arria V/Cyclone V Hard Processor System to add it to the system.
This action opens the HPS configuration window. Make the following changes:
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General
Un-check all boxes, except check the box Enable System Trace Macrocell hardware events -
AXI Bridges
Leave set to their defaults -
FPGA-to-HPS SDRAM Interface section:
Change f2h_sdram0 type to be Avalon-MM Bidirectional and 256-bit -
Resets
Leave the first two boxes uncheckedCheck Enable FPGA-to-HPS debug reset request
Check Enable FPGA-to-HPS warm reset request
Check Enable FPGA-to-HPS cold reset request -
DMA Peripheral Request
Leave set to defaults -
Interrupts
Check the box to Enable FPGA-to-HPS interrupts Leave the rest unchecked

Set the peripheral pins as follows, leave all others at their default (unused):
Ethernet Media Access Controller | EMAC1 pin to HPS I/O Set 0 | EMAC1 mode to RGMII |
Quad SPI Flash Controller | QSPI pin to HPS I/O set 0 | QSPI mode to 1 SS |
SD/MMC Controller | SDIO pin to HPS I/O Set 0 | SDIO mode to 4-bit Data |
USB Controller | USB1 pin to HPS I/O Set 0 | USB1 PHY interface mode to SDR with PHY clock output mode |
SPI Controller | SPIM0 pin to HPS I/O set 0 | SPIM0 mode to Single Slave Select |
SPI Controller | SPIM1 pin to HPS I/O set 0 | SPIM1 mode to Single Slave Select |
UART Controller | UART0 pin to HPS I/O set 0 | UART0 mode to No Flow Control |
I2C Controller | I2C1 pin to HPS I/O Set 0 | I2C1 mode to I2C |

- Scroll the table to the right until the GPIO column is visible and click the following pins:
- GPIO00
- GPIO09
- GPIO35
- GPIO48
- GPIO53-56
- GPIO61
- GPIO62

- Keep all settings in the Input Clocks sub-tab at defaults.

- Select the Output Clocks sub-tab and change the following selections from their defaults:
- In the Main PLL Output Clocks section, change the Configuration/HPS-to-FPGA user 0 clock frequency to
123.333333 MHz
- In the Peripheral PLL Output Clocks section, change the QSPI clock frequency to
370.0 MHz
- In the Main PLL Output Clocks section, change the Configuration/HPS-to-FPGA user 0 clock frequency to

- In the PHY Settings sub-tab, set:
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Memory clock frequency to
400.0 MHz
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PLL reference clock frequency to
25MHz
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Memory clock frequency to

- Select the Memory Parameters sub-tab and set the following:
Parameters -- Memory device speed grade 800.0 MHz Total interface width 32 (which will automatically update the Number of DQS groups to 4) Row address width 15 Column address width 10 Memory Initialization Options -- Memory CAS latency setting 7 ODT Rtt nominal value RZQ/6

- Select the Memory Timing sub-tab and set the values as shown in the figure below:

- Select the Board Settings sub-tab.
- In the Board Skews section change the setting to match the figure below:

- Close the HPS configuration window by clicking the Finish button.

In the System Contents tab do the following:
- Double-click in the hps_io row Export column and call it hps_0_hps_io
- Double-click in the h2f_reset row Export column and call it hps_0_h2f_reset (the default value)
- Double-click in the f2h_cold_reset_req row Export column and call it hps_0_f2h_cold_reset_req (the default value)
- Double-click in the f2h_debug_reset_req row Export column and call it hps_0_f2h_debug_reset_req (the default value)
- Double-click in the f2h_warm_reset_req row Export column and call it hps_0_f2h_warm_reset_req (the default value)
- Double-click in the f2h_stm_hw_events row Export column and call it hps_0_f2h_stm_hw_events (the default value)
- Make the following connections as show in the diagram below:
Note: to make a connection simply click on the circle at the intersection of the horizontal and vertical lines.

Next - Adding other Peripherals
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