Create DE10 Nano Processor System - ArrowElectronics/arrow-soc-workshops GitHub Wiki

• Open Platform Designer from Quartus Prime via one of the two methods below:

  • Tools -> Platform Designer menu, or
  • Click on its icon in the tool bar.  A blank project is created with a default name of unsaved.qsys.

• Do a File -> Save As … to give it the name de10nano_ghrd.qsys.

• When Saving is done, click Close.

Either type HPS in the IP Catalog search bar or, expand the Processors and Peripherals -> Hard Processor Systems and double-click Arria V/Cyclone V Hard Processor System to add it to the system.

This action opens the HPS configuration window. Make the following changes:

• General
  Un-check all boxes, except check the box Enable System Trace Macrocell hardware events

• AXI Bridges
  Leave set to their defaults

• FPGA-to-HPS SDRAM Interface section:
  Change f2h_sdram0 type to be Avalon-MM Bidirectional and 256-bit

• Resets
  Leave the first two boxes unchecked

  Check Enable FPGA-to-HPS debug reset request
  Check Enable FPGA-to-HPS warm reset request
  Check Enable FPGA-to-HPS cold reset request

• DMA Peripheral Request
  Leave set to defaults

• Interrupts
  Check the box to Enable FPGA-to-HPS interrupts Leave the rest unchecked

Set the peripheral pins as follows, leave all others at their default (unused):

Ethernet Media Access Controller	EMAC1 pin to HPS I/O Set 0	EMAC1 mode to RGMII
Quad SPI Flash Controller	QSPI pin to HPS I/O set 0	QSPI mode to 1 SS
SD/MMC Controller	SDIO pin to HPS I/O Set 0	SDIO mode to 4-bit Data
USB Controller	USB1 pin to HPS I/O Set 0	USB1 PHY interface mode to SDR with PHY clock output mode
UART Controller	UART0 pin to HPS I/O set 0	UART0 mode to No Flow Control
I2C Controller	I2C0 pin to HPS I/O Set 1	I2C0 mode to I2C

• Scroll the table to the right until the GPIO column is visible and click the following pins:
  • GPIO09
  • GPIO35
  • GPIO53

• Keep all settings in the Input Clocks sub-tab at defaults.

• Select the Output Clocks sub-tab and change the following selections from their defaults:
  • In the Main PLL Output Clocks section, change the Configuration/HPS-to-FPGA user 0 clock frequency to 100.0 MHz
  • In the Peripheral PLL Output Clocks section, change the QSPI clock frequency to 370.0 MHz

• In the PHY Settings sub-tab, set:
  • Memory clock frequency to 333.3 MHz
  • PLL reference clock frequency to 25MHz

• Select the Memory Parameters sub-tab and set the following:

  Parameters	--
  Memory device speed grade	800.0 MHz
  Total interface width	32 (which will automatically update the Number of DQS groups to 4)
  Row address width	15
  Column address width	10
  Memory Initialization Options	--
  Memory CAS latency setting	5
  ODT Rtt nominal value	RZQ/6
  Memory write CAS latency setting	5

• Select the Memory Timing sub-tab and set the values as shown in the figure below:

• Select the Board Settings sub-tab.
  • In the Board Skews section change the setting to match the figure below:

• Close the HPS configuration window by clicking the Finish button.

In the System Contents tab do the following:

• Double-click in the hps_io row Export column and call it hps_0_hps_io
• Double-click in the h2f_reset row Export column and call it hps_0_h2f_reset (the default value)
• Double-click in the f2h_cold_reset_req row Export column and call it hps_0_f2h_cold_reset_req (the default value)
• Double-click in the f2h_debug_reset_req row Export column and call it hps_0_f2h_debug_reset_req (the default value)
• Double-click in the f2h_warm_reset_req row Export column and call it hps_0_f2h_warm_reset_req (the default value)
• Double-click in the f2h_stm_hw_events row Export column and call it hps_0_f2h_stm_hw_events (the default value)
• Make the following connections as show in the diagram below:
  Note: to make a connection simply click on the circle at the intersection of the horizontal and vertical lines.

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Next - Adding other Peripherals

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