Add other DE10 Nano Peripherals - ArrowElectronics/arrow-soc-workshops GitHub Wiki

Peripherals in the GHRD are added in this section and the finishing touches are done to the Platform Designer build.

The peripherals that will be added:
Avalon MM Pipeline Bridge
JTAG to Avalon Master Bridges
System ID
On-chip Memory
JTAG UART
Interrupt Latency Counter
Push Button IP
DIP Switch IP
LED IP
In-System Sources and Probes
Interrupt Capture Module
Assign Base Addresses and Interrupt Numbers

All of the peripherals will be added before any connections are made. Because they are not connected, errors in red will appear in the Messages window. Ignore these for now, they will all go away after the connections, addresses, and interrupts are assigned at the end of this section.

Add Avalon MM Pipeline Bridge

  • Type "pipeline" in the IP Catalog search bar to filter the component library
  • In the IP Catalog under Basic Functions > Bridges and Adaptors > Memory Mapped find the Avlaon-MM Pipeline Bridge
  • Double-click it to add it to the System Contents
  • The dialog box for the component settings will be displayed
  • Check the box for Use automatically-determined address width
  • Leave the rest of the setting at their default

  • Click Finish

  • Leave the default name mm_bridge_0

  • Connect its clk port to clk_0.clk spine.

  • Connect its reset port to clk_0.clk_reset spine.

  • Connect its s0 port to the hps_0.h2f_lw_axi_master port.

Add JTAG to Avalon Master Bridges

  • Type "jtag" in the IP Catalog search bar to filter the component library.
  • In the IP Catalog under Basic Functions > Bridges and Adaptors > Memory Mapped find the JTAG to Avalon Master Bridge
  • Double-click it to add it to the System Contents.
  • Click Finish
  • Repeat this two more time to create a total of three JTAG to Avalon Master Bridges
  • Rename them as follows: fpga_only_master, f2sdram_only_master, and hps_only_master
  • Connect fpga_only_master.clk, f2sdram_only_master.clk, and hps_only_master.clk to clk_0.clk spine.
  • Connect fpga_only_master.clk_reset, f2sdram_only_master.clk_reset, and hps_only_master.clk_reset to clk_0.clk_reset spine.
  • Connect f2sdram_only_master.master to hps_0.f2h_sdram0_data port.
  • Connect hps_only_master.master to hps_0.f2h_axi_slave port.

Add the System ID Peripheral

  • Type "system id" in the IP Catalog search bar to filter the component library.
  • In the IP Catalog under Basic Functions > Simulation; Debug and Verfication > Debug and Performance find the System ID Peripheral Intel FPGA IP
  • Double-click it to add it to the System Contents.
  • In the wizard, make the following settings and change the 32 bit System ID parameter to 0xabcd3210
  • Click Finish.
  • Rename the peripheral to sysid_qsys.
  • Connect its clk port to clk_0.clk spine.
  • Connect its reset port to clk_0.clk_reset spine.
  • Connect its control_slave to fpga_only_master.master and mm_bridge_0.m0 ports.

Add Onchip Memory

  • Type "onchip" in the IP Catalog search bar to filter the component library.
  • In the IP Catalog under Basic Functions > On Chip Memory find the On Chip Memory (RAM or ROM) Intel FPGA IP
  • Double-click it to add it to the System Contents
  • Set the S1 Data width to 64 and the Total memory size to 65536 bytes
  • Leave the rest of the setting at their default
  • Click Finish
  • Leave the default name onchip_memory2_0
  • Connect its clk1 port to clk_0.clk spine.
  • Connect its reset1 port to clk_0.clk_reset spine.
  • Connect its s1 port to fpga_only_master.master and mm_bridge_0.m0 ports.

Add JTAG UART

  • Type "jtag_uart" in the IP Catalog search bar to filter the component library.
  • In the IP Catalog under Interface Protocols > Serial find the JTAG UART Intel FPGA IP
  • Double-click it to add it to the System Contents
  • Leave the default settings
  • Click Finish
  • Rename it jtag_uart
  • Connect its clk port to clk_0.clk spine.
  • Connect its reset port to clk_0.clk_reset spine.
  • Connect its avalon_jtag_slave port to fpga_only_master.master and mm_bridge_0.m0 ports.
  • Connect its irq port to hps_0.f2h_irq0 port.

Add Interrupt Latency Counter

  • Type "interrupt" in the IP Catalog search bar to filter the component library
  • In the IP Catalog under Processors and Peripherals > Inter-Process Communication find the Interrupt Latency Counter Intel FPGA IP
  • Double-click it to add it to the System Contents
  • Change the IRQ_PORT_COUNT to 3
  • Leave the rest of the setting at their default
  • Click Finish
  • Rename it ILC
  • Connect its clk port to clk_0.clk spine.
  • Connect its reset_n port to clk_0.clk_reset spine.
  • Connect its avalon_slave port to fpga_only_master.master and mm_bridge_0.m0 ports.

Add Push Button IP

-Find the PIO (Parallel I/O) Intel FPGA IP in the IP Catalog.

  • Double-click it to add it to the System Contents.
  • Set the Width to 1 and the Direction to Input
  • In the Edge capture register section check the Synchronously capture box and set the Edge Type to FALLING
  • Check the Generate IRQ box and set the IRQ Type to EDGE
  • Click Finish
  • Rename it button_pio. To do this, highlight the peripheral and either hit F2 or right-click and select Rename.
  • Double-Click in the Export column of external_connections and press the enter key to accept the default export name.
  • Connect its clk port to clk_0.clk spine.
  • Connect its reset port to clk_0.clk_reset spine.
  • Connect its s1 port to fpga_only_master.master and mm_bridge_0.m0 ports.
  • Connect its irq port to hps_0.f2h_irq0 and ILC.irq ports.

Add DIP Switch IP

  • Type "pio" in the IP Catalog search bar to filter the component library.
  • In the IP Catalog under Processors and Peripherals > Peripherals find the PIO (Parallel I/O) Intel FPGA IP
  • Double-click it to add it to the System Contents.
  • Set the Width to 2 and the Direction to Input
  • Check both boxes in the Edge capture register section and set the Edge Typ: to ANY
  • Check the Generate IRQ box and set the IRQ Type: to EDGE
  • Click Finish.
  • Rename it dipsw_pio.
  • Double-Click in the Export column of external_connections and press the enter key to accept the default export name.
  • Connect its clk port to clk_0.clk spine.
  • Connect its reset port to clk_0.clk_reset spine.
  • Connect its s1 port to fpga_only_master.master and mm_bridge_0.m0 ports.
  • Connect its irq port to hps_0.f2h_irq0 and ILC.irq ports.

Add LED IP

-Find the PIO (Parallel I/O) Intel FPGA IP in the IP Catalog.

  • Double-click it to add it to the System Contents.
  • Set the Width to 2 and the Direction to Output
  • Click Finish
  • Rename it led_pio
  • Double-Click in the Export column of external_connections and press the enter key to accept the default export name.
  • Connect its clk port to clk_0.clk spine.
  • Connect its reset port to clk_0.clk_reset spine.
  • Connect its s1 port to fpga_only_master.master and mm_bridge_0.m0 ports.

Add In-System Sources and Probes

  • Type "probes" in the IP Catalog search bar to filter the component library
  • In the IP Catalog under Basic Functions > Simulation; Debug and Verification > Debug and Performance > Intel FPGA In-System Sources & Probes find the Intel FPGA In-System Sources & Probes
  • Double-click it to add it to the System Contents
  • Change the The 'Instance ID' of this instance (optional) to RST
  • Change the Probe Port Width[0..512] to 0
  • Change the Source Port Width[0..512] to 3
  • Check the box for Use Source Clock
  • Leave the rest of the setting at their default
  • Click Finish
  • Leave the default name in_system_sources_probes_0
  • Double-Click in the Export column of sources, type "issp_hps_resets", then press the enter
  • Connect its source_clock port to clk_0.clk spine.

Add Interrupt Capture Module

  • In the IP Catalog under Other find the Interrupt Capture Module
  • Double-click it to add it to the System Contents
  • Leave the settings at their default
  • Click Finish
  • Leave the default name intr_capturer_0
  • Connect its clock port to clk_0.clk spine.
  • Connect its reset_sink port to clk_0.clk_reset spine.
  • Connect its avalon_slave_0 port to fpga_only_master.master and mm_bridge_0.m0 ports.
  • Connect its interrupt_receiver port to the hps_0.f2h_irq0 port.

Assign Base Addresses and Interrupt Numbers

Normally, IP base addresses are assigned by performing this step: From the Platform Designer menu bar, select System -> Assign Base Addresses.
BUT in this case, we need to assign the base addresses manually and lock them because the Linux device tree is expecting them to be assigned at specific addresses. To do this double-click the address in the Base column and modify it, then click the open lock icon to the left of it to lock the address.

Make the following assignments

Port Base Address Interrupt (if applicable)
mm_bridge_0 0x0000_0000 N/A
button_pio 0x0001_00c0 IRQ #1
dipsw_pio 0x0001_0080 IRQ #0
led_pio 0x0001_0040 N/A
onchip_memory2_0 0x0000_0000 N/A
jtag_uart 0x0002_0000 IRQ #2
ILC 0x0004_0000 N/A
sysid_qsys 0x0001_0000 N/A
intr_capturer_0 0x0003_0000 N/A

Specify Interconnect Requirements

There are a few directives that Platform Designer requires in order to generate the design.

  • Click on the Interconnect Requirements tab
  • Change the Limit interconnect pipeline stages to to 3
  • Change the last requirement to reflect that shown in the image below. This will allow the hps_only_master secure access to the hps memory map

Conclude settings in Platform Designer

If there are no messages in red color (or error messages), do the following:

  • Click the Generate HDL button in the bottom right of the window
  • Click Generate in the Generation window that pops up
  • Click Close in the Save System window
  • Click Close when the Generate window finishes
  • Optionally, close the Platform Designer by clicking Finish

If there are error messages in red then you very likely made a mistake or missed something. Read the message to understand the location and nature of the problem to help figure how to fix.

Next - Creating Top-Level Design

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