In order to simplify the process, we provide 3 top-level files which are specific to the SoCKit.

This section describes how to download these design files from the github repository and create the project from the ground up.

Files needed:

File	Description
sockit_ghrd_top.v	top-level Verilog file
sockit_ghrd_assign.tcl	Pin Assignment
sockit_ghrd_timing.sdc	Timing Constraints
ip sub-folder	custom IP

• The starting source files are located in a "repository" on GitHub. You need to have an environment that can execute git commands. If you have this already you can skip this step, otherwise you can install Git for Window.
  • Go to this site to download and install Git for Windows
  • Once complete launch git bash
    
    
    The shell will look like this:
    
    
    

• create and navigate to a selected directory where the project will be stored. we will use a directory named intel_trn for this workshop

    $ cd <path>/intel_trn 
  

• exec the clone command and navigate to the hdl sub-folder

    $ git clone https://github.com/ArrowElectronics/hdl.git
  
    $ cd hdl 
  

• then do the following to update the files in the working tree...

    $ git checkout R20.1_SOCKIT  
  

• The project files are located in the projects/arrow_ghrd/partial_source sub-folder

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