The kit is configured to allow the user to send data from the Intel® Arria® 10 SX FPGA to the Analog Devices® AD9371’s DAC using the JESD204B serial interface and FMC (FPGA Mezzanine Card) connectors, with the ADRV9371-W/PCBZ Evaluation Kit connected to the Critical Link MitySOM-A10S Development Kit. It is set up to send data from the AD9371’s ADC back to the Arria 10 by the same method. By attaching two RF cables, the analog outputs from the AD9371 DACs can be looped back to its ADC inputs forming a complete closed system. Using Analog Devices’ IIO Oscilloscope application on a host PC, the user can set the inputs generated by the Arria 10 and view the outputs on the return path.

The ADV9371-W/PCBZ EVB derives power from the MitySOM-A10S carrier board via the FMC connectors. The AD9528 low-jitter clock generator is available on the EVB, and its reference clock can be sourced from either an external clock or the 122.88MHz VCXO onboard the EVB. The clocks for the AD9371 converter card and the FPGA are generated by the AD9528. The FPGA’s clock is then supplied through the FMC.

The FPGA provides many capabilities in this kit. The primary means of configuring the DAC outputs and receiving the ADC inputs happens via dedicated IP blocks in the FPGA fabric. This also provides the gigabit transceivers necessary to communicate to the AD9371’s JESD204B-capable DAC and ADC.

A wired Ethernet connection between the FPGA and the host PC is used to transfer the data to and from the host IIO Oscilloscope application and the Linux OS running on the Arria-10 SoC HPS in the FPGA.

The data sent out from the FPGA to the DAC is supplied from one of two sources: the FPGA can either create a digital sine wave internally via its Direct Digital Synthesizer block (DDS), or read in an externally supplied data file. From here the digital data is packaged and sent to the JESD204B IP block inside the FPGA, where it is configured per the JESD204B standard. The serialized data is then transmitted to the DAC over an FPGA Mezzanine Card (FMC) connection on two 6.144 Gbps channels. Once the data has been received and decoded by the JESD204B DAC, the analog signals are sent to a pair of RF SMA connectors; this is defined as the transmit path.

For a closed loop system, the signals from the DAC’s SMA connectors are transmitted over RF cables to SMA connectors connected to the inputs of the ADC. The ADC takes the analog signals and converts to the serialized digital JESD204B format, then sends this back to the FPGA over the FMC connection using two additional 6.144Gbps channels; this is the receive path.

Once the data is captured in the FPGA it is sent over the gigabit Ethernet connection to the host PC running the IIO Oscilloscope application, where the results can be viewed in the time and frequency domains or as a constellation plot.  

The JESD204B interface between the Arria-10 HPS and the AD9371 ADC’s and DAC’s comprises of one (1) Transmit (TX) path and 2 Receive (RX and OS RX) paths. The following sections give a brief description of what each block does. More detailed description of the JESD204B operation can be found on the ADI website: https://www.analog.com/en/technical-articles/understanding-layers-in-jesd204b-specification.html

The TX path has three (3) possible start points:

• Using the IIO Oscilloscope application running on a host PC, along with a gigabit Ethernet cable connected from the PC to the Arria 10 SoC FPGA deposits data in the DDR4 memory to be fetched by the TX DMA block,
• Digital sine wave in the 0-500MHz range generated from the FPGA’s internal DDS frequency synthesizer blocks (TX Channel),
• Data file with a digital signal representation is selected. The TX DMA fetches that data from the DDR4 and sends it downstream. Inside the Arria 10 SX, the digital signal is converted into the JESD204B format using Analog Devices’ IP. It is then sent out across 4 lanes to an FMC connector on the Critical Link MitySOM-A10S kit at a rate of 24.576Gbps (4 lanes @ 6.144Gbps each). Refer to TX Path figure.

The data flows through the corresponding FMC connector on the ADRV9371-W/PCBZ board and into the AD9371’s multi-channel high-speed DAC where it is converted from the JESD204B standard to the proper digital format prior to being converted to analog. The DAC generates both the I (in-phase) and Q (quadrature) signals used for quadrature amplitude modulation (QAM) of the RF signal, converts it to analog and sends each signal out via SMA RF connectors connected to RG316 RF coaxial cables.

The axi_ad9371_tx_dma module uses a 128-bit memory-mapped AXI4 source interface, which is a slave to the HPS; and a 128-bit streaming AXI4 destination master interface. It has a 2KB FIFO which holds up to 16 bursts, where each burst can be up to 128 bytes.

The avl_ad9371_tx_fifo module sits between the TX DMA and the TX UPACK modules. It can optionally be bypassed. It accepts data from two (2) sources. The first and primary source is the 128-bit DMA data. The secondary and optional source is the Fabric’s DDR4 controller. Each of the input paths has a FIFO that is 4K deep and 128-bit wide and can handle bursts of 64 words. See JESD204B Tx Path figure.

The axi_ad9371_tx_upack module takes a 128-bit data bus. It unpacks and demuxes it and sends it downstream to the axi_ad9371 module to be split into four 32-bit paths to the 4 TX channels.

The axi_tx module contains 4 copies of the axi_tx_channel module. Each of these 4 channel modules receives a 32-bit data pipe from the TX UPACK module representing two (2) I data and two (2) Q data channels. The user, under processor control, can select one (1) of three (3) data sources to pass through. The module does the following tasks:

• Generate DDS data under processor control,
• Generate a 32-bit pattern under processor control,
• Pass the data from the TX UPACK module,
• Performs IQ correction with coefficients provided under processor control to the data past the multiplexer.

The jesd204_tx inside of the ad9371_tx_jesd204 module handles data preparation before it goes to the SERDES transceivers in the link layer. This module contains 4 lane submodules where each one handles one (1) 32-bit lane of data to a corresponding transceiver. The lane submodule has optional features, under program control, to scramble the data in order to reduce EMI. If the scrambling is selected in the TX path, the descrambling should be selected in the RX path. It generates the lane alignment character along with 8B/10B encoding. It also creates and maintains link synchronization. See JESD204B Tx Path figure.

Additional detailed information can be found here

This module contains the PHY in the form of four (4) SERDES transceivers which convert the 32-bit parallel data into a 6.144Gbps serial stream which goes to the ADR9371 DAC.

The analog RF signals flow through the two coaxial cables from the TX path and back into the ADRV9371-W/PCBZ board through two additional SMA RF connectors routed to the AD9371’s 2-channel ADC. The signal is then sampled and digitized and converted back into the JESD204B standard. The Observation Receiver (OS RX) is not used in this demo.

Data is sent back to the Arria 10 SX along 2 Serdes lanes at a rate of 6.144Gbps per lane (12.288Gbps total) across the FMC connector where it is decoded by Arria 10 FPGA IP blocks.

The received data is then sent to the host PC over the gigabit Ethernet connection. Using the ADI IIO Oscilloscope graphical user interface application on the host, the received data can be viewed in the time domain, frequency domain or as a polar plot.

The RX JESD LINK (PHY) contains two (2) Serdes transceivers running at 6.144Gbps. This pair of transceivers gets its serial data from the AD9371 ADC and sends a 32-bit parallel bus to the RX JESD IP block.

The RX JESD IP has two (2) lanes for processing data from the Serdes transceivers. Each of the lanes handles link synchronization, lane alignment, character replacement, and optionally descrambling the data (if scrambled in the TX). The data goes through an elastic buffer before it exits to the RX Channel in the AD9371 IP block.

Additional detailed information can be found here

The two (2) lanes each drive a pair of rx_channel blocks. This pair of channels splits the 32-bit incoming data into 16-bit for the I, and 16-bit for the Q processing. The RX CHANNEL has an optional DC filter and optional IQ correction circuit.

The RX PACK module takes the four (4) 16-bit data streams, along with their associated valid signals, and packs them into a 64-bit bus to most efficiently present them to the RX DMA.

The RX DMA module contains a 256x64 FIFO which can process up to 16 bursts of 128-bytes/burst. The DMA sends data from the FIFO to the DDR4 memory on the board.

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