ADRV9002 Platform Board Architecture - ArrowElectronics/arrow-adi-intel-psg GitHub Wiki
The ADRV9002 Platform uses 3 boards to implement a CMOS or LVDS interface between the Intel® Arria®-10's HPS and the ADRV9002.
Critical Link MitySOM-A10S Development Kit
Critical Link MitySOM-A10S System On Module
Analog Devices ADRV9002NP/W1/PCBZ Development Board
The Critical Link MitySOM®-A10S Development Kit is comprised of 2 boards, a SOM and a carrier board. The MitySOM-A10S SOM plugs into the carrier board via 2 connectors, a hirose 144-pin, and a VITA-57 HPC FMC connector.
The major components of the Critical Link MitySOM-A10S Development Kit are identified by numbers:
Ethernet RJ-45 interface
USB-OTG interface
USB-serial interface
FMC loopback interfaces supporting gigabit transceivers, LVDS and single-ended I/Os
PCIe x8 edge connector (optional). Dev kit with this option P/N: 80-001181
Power management
The Critical Link MitySOM-A10S system on a module featuring the Intel Arria® 10 SoC (system on a chip) with dual core Arm® Cortex® A9 32-bit RISC processors is a highly-configurable, medium-form-factor module. In addition to the processor, the module includes on-board power supplies, two DDR4 RAM memory subsystems, optional eMMC, micro SD card, a fan controller, RTC, a USB 2.0 on the go (OTG) port, and a temperature sensor. The MitySOM-A10S provides a complete and flexible CPU infrastructure for highly integrated embedded systems.
The major components of the Critical Link MitySOM-A10S are identified by numbers:
- SX Processor:
- Dual ARM Cortex A9 MPU
- Up to 1500 MHz max clock speed
- Dual NEON SIMD Coprocessors
- 32KB L1 Program Cache (per core)
- 32KB L1 Data Cache (per core)
- 512 KB L2 Cache (shared)
- Up to 138 User FPGA I/O pins
- Up to 4 additional HPS Only Pins
- Twelve 8 Gbps Transceiver Pairs
- FPGA Fabric:
- Up to 480K Logic Elements (LE)
- 460MHx Global Clock
- Up to 28Mb M20K Memory
- Up to 4.3Mb MLAB Memory
- Up To 1368 Floating Point Multipliers
- Up To 2736 Fixed Point Multipliers
- 32 Global Clock Networks
- Twelve 8Gbps Transceivers
- 1 x8 PCIe Hard IP Block (Up to Gen 3)
- 1 x4 Bonded Set
Bank 1: Up to 4GB DDR4
- 32-bits wide
- 8.5GBps burst transfer rate shared with HPS
Bank 2: Up to 2GB DDR4
- 16-bits wide
- 4.24GBps burst transfer rate
JTAG connector on-module
On board MicroSD Card Interface (bottom side)
Optional eMMC
Hirose 144-pin Board-to-Board Connector
FMC (HPC) Board-to-Board Connector
- Integrated Power Management
- On Board USB 2.0 PHY
- On Board RTC
- 2 On-Board Temperature Sensors
- Power, Reset and Clock Management
The EVAL-ADRV9002 development board comes in 2 flavors, one is Low Band (EVAL-ADRV9002NP/W1/PCBZ) which supports a RF frequency range of 30MHz to 3GHz, and one High Band (EVAL-ADRV9002NP/W2/PCBZ) which supports a RF frequency range of 3GHz to 6GHz. Two power rails enter the board from the FMC connector, 12VDC and 3.3_AUX. The ADP5056 is used to generate 3 other rails; 1.8V, 1.3V, and 1.0V. Each of these rails has an analog and a digital version where each can have their voltages and current consumption monitored by an ADM1293 via I2C bus.
The reference clock can come from an on-board 38.4MHz TCXO, or via J501 SMA connector. These 2 clock sources go thought an RF switch (HMC849A). The switch select is controlled by a mechanical slide switch (S501). The selected clock is then distributed to the ADRV9002 and FPGA usingthe ADCLK944 clock fanout buffer.
A MultiChip Synchronization (MCS) signal source can be brought in via SMA J502 and distributed, by another ADCLK944, to the ADRV9002 and the FPGA..
Full descriptions of these products are available in their respective data sheets, which must be consulted when using the corresponding evaluation board.
ADRV9002 - RF Transceiver
ADP1762 - Low Noise CMOS LDO
ADM1293 - Digital Power Monitor with PMbus
EEPROM
38.4MHz TCXO
ADP5056 - Triple Buck Regulator Integrated Power Solution
LTC3621 - 17V Buck Regulator
ADCLK944 4 Output LVPECL Clock Fanout Buffer
HMC849A - High Isolation SPDT Switch, DC to 6GHz
AD8045 - Ultralow Distortion, high speed OpAmp
ADP1755 - 1.2A LDO
LPC FMC Connector
SMA - MCS Input
SMA - DEV_CLK Input
Clock Source Select slide switch
SMA - TX2 Output
SMA - Rx2A Input
SMA - LO2 Input
SMA - Rx2B Input
SMA - Rx1B Input
SMA - LO1 Input
SMA - Rx1A Input
SMA - Tx1 Output
The block diagram of the EVAL-ADRV9002NP/Wx/PCBZ board (below) shows the major components.
