The Golden Hardware Reference Design 24.2 - ArrowElectronics/Agilex-5 GitHub Wiki

The Golden Hardware Reference Design (GHRD) for the AXE5-Eagle Development Platform provides a starter reference design. It includes a Platform Designer reference design that maps several HDL-based peripherals to the HPS (Hard Processor System) and the ARM Cortex-76/Cortex-A55 processors. This design is intended as a starting point for new designs.

1. Prerequisites
2. Release Contents
3. Overview
4. Build the Golden Hardware Reference Design
5. Validate with System Console

• Intel Quartus Prime Pro Edition v24.2

The Golden Hardware Reference Design is an important part of a bootable Linux system and consists of the following components:

• Hard Processor System (HPS)
  • Dual core Arm Cortex-A76 processor
  • Dual core Arm Cortex-A55 processor
  • HPS Peripherals:
    • SDMMC
    • EMAC
    • USB UART
    • I2C
    • USB 3.1 (2.0 mode)
• Multi-Ported FrontEnd(MPFE) for HPS External Memory Interface (EMIF)
• FPGA Peripherals connected to Lightweight HPS-to-FPGA (LWS2F) AXI Bridge and JTAG to Avalon Master Bridge
  • HDMI Video output
  • Two user push-button inputs
  • Two user DIP switch inputs
  • Four user I/O for RGB LED outputs
  • JTAG UART
  • System ID
• FPGA Peripherals connected to HPS-to-FPGA (S2F) AXI Bridge
  • FPGA External Memory Interface (EMIF)

The GHRD is constructed with hierarchy. There is a top level which instantiates multiple subsystems. These include the following subsystems:

• Board
• Clock
• HPS
• EMIF
• Peripheral
• Video

This section presents the address maps as seen from the MPU .

The three FPGA windows in the MPU address map provide access to 256 GB of FPGA space. First window is 1 GB from 00_4000_0000, second window is 15 GB from 04_4000_0000, third window is 240 GB from 44_0000_0000. The following table lists the offset of each peripheral from the HPS-to-FPGA bridge in the FPGA portion of the SoC.

The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0x00_2000_0000, is listed in the following table.

There are three JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGA fabric, and another for accessing SDRAM attached to the HPS through the FPGA-to-SDRAM Interface and another for FPGA fabric to SDRAM. The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface.

Open a shell (Nios V Command Shell for Windows)

For Linux only, specify a path to the Quartus installation

    $ export PATH="<path to >/intelFPGA_pro/24.2/quartus/bin64:$PATH"

Create a project directory

    $ mkdir agilex_5
    $ cd agilex_5

This can be built under Windows or Linux.

Clone the repository.

    $ git clone -b QPDS24.2.0.40_REL_GHRD https://github.com/ArrowElectronics/ghrd-socfpga ghrd-socfpga
    $ cd ghrd-socfpga/axe5_eagle_ghrd

Open Quartus and load the Project

    $ File --> Open Project. Select axe5_eagle_top.

Correct the path to the External Memory Interface preset file

    $ Open agilex_5/ghrd-socfpga/axe5_eagle_ghrd/ip/emif_subsystem/emif_subsystem_emif_ph2_0.ip in a text editor. Navigate to line 2659. Modify the path to the emif.qprs memory preset file.

    $ Open agilex_5/ghrd-socfpga/axe5_eagle_ghrd/ip/hps_system/hps_system_emif_hps_ph2_1.ip in a text editor. Navigate to line 2634. Modify the path to the emif.qprs memory preset file.

Compile the Quartus project

    $ Processing --> Start Compilation

The following file is created:

• agilex_5/ghrd-socfpga/axe5_eagle_ghrd/output_files/axe5_eagle_top.sof

This section presents how to add the u-boot First Stage Boot Loader (FSBL) to the SOF file. This creates a new SOF file which can be used to configure the device through the Quartus Programmer.

Download First Stage Boot Loader (FSBL) and copy it into the agilex_5/ghrd-socfpga/axe5_eagle_ghrd/output_files folder

    $ cd agilex_5/ghrd-socfpga/axe5_eagle_ghrd/output_files/
    $ quartus_pfg -c axe5_eagle_top.sof  axe5_eagle_top_hps.sof -o hps_path=u-boot-spl-dtb.hex

System Console is an FPGA debugging tool included in the Quartus Prime package.

This page demonstrates how to use the System Console to control the development board peripherals:

• Read the System ID peripheral
• Turn RGB_LED2 on and off
• Read Push button and DIP switch values
• Write/read the LPDDR4 SDRAM connected to the FPGA

All the interaction happens between FPGA and System Console running on the host PC. There is no software running on HPS.

The following components are required for the demo:

• AXE5-Eagle (TEI0185) development board,
• 12VDC 40W power supply
• Arrow-USB-Blaster (TEI-0004-02) for downloading to the FPGA

Depending on the kit revision, additional components may need to be obtained. Please click on this link to review.

• Plug the Arrow-USB-Blaster (TEI0004-02) into J34 with the USB connector facing to the right.

• Connect the power supply to the AXE5-Eagle J29 barrel connector
• Plug the AC-DC adapter into an AC outlet

Use the Intel Download cable when programming the AXE5-Eagle board from a Linux environment.

The FPGA JTAG chain will expose 1 or 2 endpoints when auto-detected from the programmer. Follow the appropriate instructions to program the Agilex 5 FPGA for either scenario.

Open the Quartus Programmer

    $ Tools --> Programmer

Detect the JTAG chain

    $ Processing --> Auto Detect

Option 1: One Device

Option 2: Two Devices

Select the A5EC065BB32AE4SR0 device in the topology diagram

Program the device

    $ Edit --> Change File. Select output_files/axe5_eagle_top_hps.sof
    $ Click the 'Program/Configure' check box.
    $ Processing --> Start

This will take a few seconds to complete.

Open System Console

    $ Tools --> System Debugging Tools --> System Console

List all JTAG masters

    $ get_service_paths master

Select and open the fpga_only_master

    $ set fpga_only_master [lindex [get_service_paths master] 0]
    $ open_service master $fpga_only_master

Read the System ID peripheral

    $ master_read_32 $fpga_only_master 0x08000000 1

Read the Push Button PIO

    $ master_read_32 $fpga_only_master 0x08000010 1

Press FPGA_PB2 and read again

    $ master_read_32 $fpga_only_master 0x08000010 1

Read the DIP Switch PIO

    $ master_read_32 $fpga_only_master 0x08000020 1

Change the position of FPGA_SW3 and read again

    $ master_read_32 $fpga_only_master 0x08000020 1

Illuminate RGB_LED2 - red

    $ master_write_32 $fpga_only_master 0x08000050 0x03

Illuminate RGB_LED2 - green

    $ master_write_32 $fpga_only_master 0x08000050 0x05

Illuminate RGB_LED2 - blue

    $ master_write_32 $fpga_only_master 0x08000050 0x06

Turn off RGB_LED2

    $ master_write_32 $fpga_only_master 0x08000050 0x07

Select and open the fpga_emif_only_master

    $ set fpga_emif_only_master [lindex [get_service_paths master] 1]
    $ open_service master $fpga_emif_only_master

Write and read FPGA LPDDR4 memory

    $ master_read_32 $fpga_emif_only_master 0x00000000 1

    $ master_write_32 $fpga_emif_only_master 0x00000000 0x12345678

    $ master_read_32 $fpga_emif_only_master 0x00000000 1

For more information about System Console, refer to

• Introduction to System Console
• Analyzing and Debugging Designs with the System Console.
• System Console Whitepaper