xSPI Memory Controller

SLL successfully support a wide range of Arrow and Altera customers using our xSPI memory controller IP since 2017. We are the only dedicated xSPI IP design house, as this is our core business since 2016. Our xSPI IP is already contracted into more than 12 high volume ASIC dies. Our xSPI IP's provide higher assurances for FPGA projects, fully supported by expert staff.

For all popular Altera FPGA device families

• Agilex 3, Agilex 5, Cyclone 10 GX, Cyclone 10 LP, MAX 10, Cyclone V, …

• The production version of our IP employs the hard PHY cores inside Agilex 3, Agilex 5 and Cyclone 10 GX devices:

  • High signal integrity margins over full temperature range
  • Support up to 200 MHz DDR x16 xSPI PSRAM
  • Supports accessing two x16 xSPI PSRAM devices in parallel to create x32 wide data path

• ~100% code coverage testing of memory controller core to reduce project risk:

  • SLL's xSPI Initiator core (which forms the heart of the xSPI Initiator core for Altera FPGA) has been licensed for use in more than 12 high volume ASIC dies

• Request trial access for full x8/x16/x32 200 MHz DDR support

For all memory vendors devices

Vendor	Devices
AP Memory	IoT x8/x16 PSRAM
Everspin	xSPI x8 STT-MRAM
ISSI	x8 Octal Flash, x8 Octal RAM, …
Infineon	x8 SemperFlash, x8 HyperFlash, x8/x16 HyperRAM
GigaDevice	x8 JEDEC Profile 1.0 NOR Flash
Micron	x8 Xccela Flash
Macronix	x8 xSPI Profile 1.0 OctaFlash
Winbond	x8/x16 HyperRAM
XC Memory	x8 PSRAM

SLL supports all LVCMOS I/O 1.2V, 1.35V, 1.8V, and 3.3V I/O memory device variants.

Understanding the relationship between various memory vendor product families and the xSPI standard

JEDEC xSPI is a standard that provides a unifying wrapper around similar, but otherwise binary incompatible, NOR Flash and PSRAM device families. Some memory devices are xSPI Profile 1.0 compliant, others are xSPI Profile 2.0 compliant, others are similar to, but not compatible with xSPI Profile 1.0 or 2.0. To be clear, two xSPI memory devices that are xSPI Profile 1.0 compliant may in fact be binary incompatible, with different command codes and timing behaviour.

xSPI Profile	CMD-ADDR-DATA	Compatible with
SPI Mode (optional)	1S-1S-1S	A minimal subset of SPI @ <= 50 MHz
xSPI Profile 1.0 (optional)	8D-8D-8D	OctaFlash, OctalFlash, SemperFlash with xSPI interface, STT-MRAM and Xccela Flash
xSPI Profile 2.0 (optional)	8D-8D-8D	HyperFlash 2.0, SemperFlash with HyperBus interface, HyperRAM
N/A	8D-8D-8D	IoT PSRAM, Octal RAM
N/A	8D-8D-16D	HyperRAM 3.0, IoT PSRAM

Some xSPI compatible memory devices only support xSPI Profile 2.0 mode of operation, others support {SPI and xSPI Profile 1.0} modes of operation. All memory devices support power on in 8D-8D-8D mode of operation. SLL recommends FPGA customers select memory device product order codes that power on in 8D-8D-8D mode.

SLL's xSPI Memory Controller supports all the above memory device variants. Furthermore, SLL has physically tested our memory controller is compatible with all the above memory device families.

In the rest of this section, when we refer to xSPI we implicitly imply all the xSPI and xSPI-like memory devices above.

Effective memory bandwidth vs wire-speed memory bandwidth

All the above memory devices follow the usual serialisation of {Command - Address - Wait States - Data Payload} over the same IO[7:0] / IO[15:0] pins. All memory transfer requests are received and processed sequentially, one at a time, in-order. xSPI memory devices can process at most one memory transfer request at a time.

The wire speed bandwidth of an xSPI memory channel is calculated as the data path width (e.g. IO[7:0]) x double data rate x clock speed of the memory channel. So a x8 PSRAM operating at 200 MHz has (1 byte wide data path x 2 data unit intervals per clock cycle x 200 MHz memory channel clock speed) = 400 Megabyte/s wire speed. This is the bandwidth that is reported by memory device data sheets.

However, the effective memory bandwidth of xSPI devices is always less than the wire speed memory bandwidth. The effective memory bandwidth is strongly dependent on the payload / burst length of the memory transfer request. The longer the payload, the closer the effective memory bandwidth approaches the wire speed bandwidth of the memory channel. However, some xSPI memory types, such as Pseudo-SRAM (PSRAM) must periodically self-refresh the contents of the SDRAM to avoid memory corruption, which in turn limits the maximum burst length.

SLL has implemented an effective memory bandwidth calculator that estimates the bandwidth based on a DMA Bus Initiator that can sustain 2 outstanding memory transfer requests to SLL's xSPI memory controller: The first memory transfer request being issued to the memory device, and the second memory transfer request being queued in the memory controller. There is typically no benefit to a DMA bus initiator sustaining more than 2 outstanding memory transfer requests with xSPI memory devices.

SLL's effective memory bandwidth calculator takes into account the data path width, clock speed, the optimal initial access latency (wait states) between the last byte of address and the first byte of the data payload for a given clock speed, temperature rating, any self-refresh requirements, and the number of wait states required between memory transfer requests. These parameters are somewhat similar between memory device variants.

These estimated effective memory bandwidth calculations should be considered as upper-bound performance estimates:

• In practice, for frame buffer like applications, you should modestly over provision memory bandwidth for your application to provide a margin for error.
• For soft-core CPU applications, you should always enable both instruction and data caches. Where possible prefer larger cache sizes with 8 Kilobyte or larger capacity. Where possible, select the largest supported cache-line length (e.g. 32-bytes) and write back mode of operation. Increasing the cache size capacity tends to reduce the amount of cache-line misses, with typically at most one outstanding cache-line miss being issued at a time. Where viable, map the stack segment to on-chip SRAM to significantly reduce the amount of dirty cache-lines written to PSRAM.

The effective memory bandwidth of most PSRAM devices are some-what comparable. Please email SLL if you require effective memory bandwidth requirements for a specific memory device model.

x8 PSRAM @ 100 MHz DDR

PSRAM devices autonomously perform self-refresh operation inbetween memory transfer requests. This rate of self-refresh is dependent on the current temperature of the memory device.

Consequently, the maximum burst length of PSRAM devices is constrained by the maximum wall-clock time of a memory transfer request operation. Given the self refresh of the PSRAM is incrementally performed row by row between memory transfer requests, the maximum burst length of a memory transfer request issued to a PSRAM device depends on multiple factors:

• The faster the clock speed, the more bytes that can be transmitted before a refresh operation is performed.
• The wider the data path, the more bytes that can be transmitted before a refresh operation is performed.
• The higher the maximum supported operating temperature, the less bytes that can be transmitted before a refresh operation is performed.

Typically, all x8 PSRAM memory devices operating at 100 MHz DDR at -40’ to +80’C have a maximum burst length of 256 bytes. This is why the graph below stops at a burst length of 256 bytes. The blue bar represents read operations, and the green bar implements write operations.

The free trial version of SLL's xSPI memory controller in this Arrow Electronics repository for Agilex is limited to 100 MHz DDR clock speed, and therefore only supports a maximum burst length of 256 bytes. Where as the full version of SLL's xSPI Memory Controller for Agilex and Cyclone 10 GX supports 200 MHz DDR and therefore can support far longer burst lengths.

Note: The full version of SLL's xSPI memory controller requires precise mapping of the xSPI signals to Altera's Agilex and Cyclone 10 GX pins. Do not rely on the schematics of any openly published reference designs for the correct pinout mapping. Please email SLL and ask for pinout guidance before you start your PCB design to avoid board re-spins.

x8 PSRAM @ 200 MHz DDR

Typically, all x8 PSRAM memory devices operating at 200 MHz DDR at -40’ to +80’C have a maximum burst length of 1024 bytes.

You can see that the effective memory bandwidth utilisation improves up to 95.7% with 1024 byte bursts. This makes PSRAM ideal for frame-buffer applications.

Commercial customers can request trial access for full x8 200 MHz DDR support here

x16 PSRAM @ 200 MHz DDR

Typically, all x16 PSRAM memory devices operating at 200 MHz DDR at -40’ to +80’C have a maximum burst length of 2048 bytes.

A single instantiation of the full version of SLL's xSPI Memory Controller supports x16 PSRAM devices.

SLL also supports chaining two xSPI memory controller instantiations in parallel to support a 32-bit wide data path. In particular we can split a single AXI4 memory transfer request over two controllers which doubles the maximum burst length and approximately doubles the maximum effective memory bandwidth of both read and write operations.

Commercial customers can request trial access for full x16 and x32 200 MHz DDR support here

--

Images and text © Synaptic Laboratories Ltd. 2025. All rights reserved.