Overview
Quick Start Guide
Build Instructions
Reference Documents

The PCIe Endpoint example design for the AXE5-Eagle development kit demonstrates communication over a PCIe interface between a Host PC and an Agilex™ 5E FPGA device. The example design was automatically created in Platform Designer and underwent minor modifications to function on the AXE5-Eagle development kit.

PCI Express is a point-to-point, serial interconnect bus with protocol stack that includes Transaction, Data Link and Physical Layers. The protocol is scalable – from 1 lane to 32 lanes per link, with data on the link serialized and sent from one device to another. It uses differential signaling with complementary pair of signals for transmit and receive sides and uses packet-based transactions. You can use the IPs for PCI Express available in the Quartus® Prime Pro Edition catalog to implement PCI Express in your designs. A typical topology is shown in the diagram below.

The Agilex™ 5 FPGA includes GTS high-speed transceivers. The associated GTS AXI Streaming IP is designed to implement a PCIe 4.0 interface in the Agilex 5 device family. The IP configuration support for Agilex 5 device families are detailed in the following table.

The GTS AXI Streaming IP is built on the PCIe Hard IP block. It consists of the following major sub-blocks:

• PCIe Hard IP (HIP) which consist of PMA, PCS, PIPE, PCIe controller, and PLD interface.
• Soft logic blocks in the FPGA fabric to serve as an adapter between User Logic and HIP to allow user to configure the IP and access to the features supported by HIP.

The PCIe Transaction Layer Packets are connected to the User Logic via AXI streaming ports

The GTS AXI Multichannel DMA IP for PCI Express (GTS AXI MCDMA IP) allows you to implement Multichannel DMA using the industry-standard AXI interface protocol. The GTS AXI MCDMA IP interfaces with the GTS AXI Streaming IP for PCI Express (GTS AXI Streaming IP). It facilitates streamlined and high-performance data transfers by furnishing independent DMA channels that operate seamlessly over the underlying PCIe link connecting the host and the device. In the example design, the MCDMA IP is part of the User logic. A functional block diagram of the MCDMA IP is shown below.

User mode and supported user interfaces

Multichannel DMA

• H2D AXI-S/MM Manager interface
• D2H AXI-S/MM Subordinate interface
• PIO AXI4-Lite Manager interface
• User MSI-X interface
• User FLR interface

Bursting Master (BAM)

• BAM AXI4 Manager interface

Bursting Slave (BAS)

• BAS AXI4 Subordinate interface
• User MSI interface

The MCDMA IP facilitates three different options for data transfers.

MCDMA IP transfers

• Concurrent DMA controllers in the MCDMA IP transfer data between Host and Endpoint memory.

AXI4-Lite PIO Manager

• Part of the MCDMA logic
• Non-burst TLP packets are transferred to the AXI4-Lite port

Bursting Master (BAM)

• Host PC TLP bursts are converted by the BAM into AXI-MM burst read and write transactions to User logic.This will bypass the MCDMA logic in the MCDMA IP.

Bursting Slave (BAS)

• User logic initiated AXI-MM transfers are translated to PCI Express TLP read and write packets.

The Demo was automatically created in Platform Designer from the Example Designs tab of the MultiChannel DMA for PCI Express IP Parameter Editor. The Parameter Editor allows a number of different designs to be created, each testing a different functional mode of the MCDMA IP. In this example, the Agilex™ 5 FPGA is configured as a Gen 4 x 4 PCIe Endpoint and supports the following PCI Express transfer types.

• AXI-MM DMA
• PIO non-burst, reads and writes

A block diagram of the design is shown below.

The example design specifies two BARs. BAR0 and BAR2. BAR0 is used to access the internal configuration and status registers of the MCDMA IP. BAR2 maps the user logic to the host PC memory map.

The Host PC can access logic attached to the AXI4-Lite interface with non-burst CPU read and write transactions.

Host to Device (H2D) or Device to Host (D2H) transactions are initiated by the MCDMA IP. They transfer data using burst cycles between Host PC and FPGA memory.

This Quick Start Guide describes the hardware and software setup needed to run the PCIe Endpoint demo.

In this demo configuration, a PCIe Root port communicates with the AXE5-Eagle board as an Endpoint. Both PIO and DMA transactions are demonstrated.

To run the PCIe Endpoint demo, follow the steps below:

1. Prerequisites
2. Convert the Arrow Blaster to a USB-Blaster III
3. Configure the Board for the Demo
4. Flash the FPGA configuration file
5. Test The Example Design

• Host system with a PCIe 4.0 x4 slot.
• Operating System: Ubuntu 24.04.1 LTS
• Kernel: 6.6x. Rollback required
• Quartus Prime Pro Programmer (Windows or Linux)

The following components are required for the demo:

• AXE5-Eagle (TEI0185-02 or -03) development board
• 12VDC 40W power supply
• Arrow-USB-Blaster (TEI-0004-02) for downloading to the FPGA
• 1 x micro-USB Cable (for the Arrow Blaster)
• Host PC with PCIe x4 slot
• PCIE 4.0 Extension Cable

The MSEL2 and MSEL1 DIP switches need to be set to the ON position (left) for Boot from QSPI configuration.

Turn off the Host PC

• Open the Host PC and install the PCIE 4.0 Extension Cable in an available PCIe slot.

• Plug the AXE5-Eagle gold fingers into the PCIE 4.0 Extension Cable connector.

• Plug the Arrow-USB-Blaster (TEI0004-02) into J34.

• Connect the power supply to the AXE5-Eagle J29 barrel connector

• Plug the AC-DC adapter into an AC outlet

Turn on the Host PC

• Download the FPGA SOF image pcie_ed.sof

Select the SOF file. Edit --> Add File. Navigate to the sof file. Press Open.

Check the Program/Configure check box. Press Start. Wait till progress is 100%.

Perform a warm reboot for the host system once the Agilex 5 FPGA is successfully configured.

Check the enumeration of the PCIe Endpoint device ( AXE5-Eagle Development Kit) on the host system by running the lspci –d 1172: command in a Linux terminal.

Expected result:

    $ Unassigned class [ff00]: Altera Corporation Device 0000 (rev 01)

Download the example source code

Open a Linux terminal. cd to the compressed file. Unzip the file.

Installing the Required Kernel Version for Ubuntu v24.04

Set the Boot Parameters

Install the Linux Kernel Driver

Follow the steps for the UIO driver installation only.

Build and Install the User Space Library

Build the Reference Application

BDF is represented by B:D:F as hex [HHHH:BB:DD.F] where

HHHH represents the Host Domain, BB represents the Bus or Slot, DD represents the Device and F represents the Function.

    $lspci -tv | grep 'Altera'

Expected result for example

    $+-[02.0] ----00.0  Altera Corporation Device

Place 02 in the BB position of the BDF format to get a BDF of [0000:02:00.0].

PIO Test

AXI-MM DMA (AXIMM DMA) Test Use a payload length of 16384, not 32768.

• Quartus Prime Pro 25.3 required.

The Demo was automatically created in Platform Designer from the Example Designs tab of the GTS AXI MultiChannel DMA for PCI Express IP Parameter Editor. The Parameter Editor allows a number of different designs to be created, each testing a different functional mode of the MCDMA IP. In this example, the Agilex™ 5 FPGA is configured as a Gen 4 x 4 PCIe Endpoint and supports the following PCI Express transfer types.

• Avalon-MM DMA
• PIO non-burst, reads and writes

A block diagram of the design is shown below.

To recreate the example design, use the following steps in the User Guide with specifics defined for the AXE5-Eagle board.

• In the Quartus® Prime Pro Edition software, create a new project by clicking File → New Project Wizard. Click Next.

• Select Empty Project type and specify the Directory, Name, and Top-Level Entity. Click Next.

• Specify the Family, Device & Board Settings as follows: Select Family: Agilex™ 5 (E-Series/D-Series). Select Target Device = A5ED065BB32AE4SR0 Click Finish.

• Select from Tools → IP Catalog to open the IP Catalog

• Select GTS AXI Multichannel DMA IP for PCI Express (Library → Interface Protocols → PCI Express → GTS AXI Multichannel DMA IP for PCI Express) and then click Add.

• In the New IP Variant dialogue box, specify a top-level name for your new custom IP variation and the directory for it. The IP Parameter Editor saves the IP variation settings in a file named <your_ip>.ip. Click Create.

The IP Parameter Editor appears as shown in the figure below. The GTS AXI Multichannel DMA IP for PCI Express features IP Settings, PCIe Settings, and Example Designs tabs, enabling you to configure your custom IP variation quickly.

• Select the MCDMA sub-tab under the PCIe Settings Tab. Set the User Interface as AXI-MM

• Select the Synthesis check box and set the selected Example Design to AXI-MM DMA.
• Set the System Settings Hard IP Mode to be Gen4 x4 Interface 256 bit

• Set the Data Width to 256.
• Click the Generate Example Design button.
• Select OK.

Specify the pin locations and I/O standards.

• Download the pcie_assignments.tcl file. Save it in the generated Example Design project directory.

• Open the console. View --> Console

• In the console window enter 'source pcie_assignments.tcl' at the prompt. Press enter.

• Processing --> Start Compilation

GTS AXI Multichannel DMA IP for PCI Express* User Guide

Multi Channel DMA IP for PCI Express* Design Example User Guide