Nios Vg Boot Copier Reference Design AXE5000 26.1 - ArrowElectronics/Agilex-5 GitHub Wiki

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Quick Start Guide
Build Instructions

Quick Start Guide

This Quick Start Guide describes the hardware and software setup needed to run the Nios® V/g Boot Copier reference design.

To run the Yocto Linux Command-Line demo, follow the steps below:

  1. Overview
  2. Theory of Operation
  3. Install the Quartus Prime Pro Programmer
  4. Configure the Board for the Demo
  5. Flash the FPGA configuration file.
  6. Run the Demo

Overview

The Nios V/g processor is a soft-core RISC-V processor implemented in many of the Altera FPGA family fabrics. Unlike a Hard Processor System (HPS), it has no dedicated boot ROM or autonomous boot hardware. The Agilex 5 family of devices uses a Secure Device Manager (SDM) to configure the fabric. When the SDM releases the processor from reset, it begins executing from wherever its reset vector points. This makes the boot strategy entirely the responsibility of the system designer.

A common and effective approach for larger embedded designs is the bootcopier pattern: a small, self-contained application pre-initialised into On-Chip Memory (OCM) as part of the FPGA bitstream, which runs immediately at reset and copies the main user application from external QSPI flash into fast external DRAM before jumping to it. This pattern is relevant for several practical reasons. OCM is limited in size and cannot hold a large application. DRAM offers far greater capacity and bandwidth for a full-featured embedded application, and QSPI flash provides non-volatile persistent storage that survives power cycles. The bootcopier bridges all three: it lives in OCM, reads from flash via the SDM mailbox interface (the only path to QSPI available to the Nios V on Agilex 5), copies the application to DRAM, and hands off execution cleanly. Understanding how the bootcopier works — including the flash record format, the toolchain steps that produce it, and the cache coherency requirements when the Nios V/g instruction and data caches are enabled — is essential for any engineer deploying a larger Nios V-based application on Agilex 5.

This reference design demonstrates a Nios® V/g processor copying an application payload from QSPI flash to HyperRAM. When this is complete, it determines the entry point of the application, and executes it from HyperRAM. The Nios V/g processor has optional instruction and data caches that facilitate efficient execution from HyperRAM.

The reference design includes

  • Nios® V/g Microcontroller
  • Onchip RAM (64KB)
  • SLL xSPI (HyperRAM) memory controller
  • System ID peripheral
  • Mailbox Client
  • Push-Button
  • RGB LED
  • Light Weight UART

Theory of Operation

Reference design block diagram. Power-on sequence of events.

SLL xSPI IP description and features

Nios description and features

Configure the Board for the Demo

The following components are required for the demo:

  • AXE5000 (TEI0181) development board,
  • USB C Cable

Assemble the Hardware

  • Plug the USB Cable into J9, the USB C connector.

Flash the FPGA Configuration File

Open the Quartus Programmer

    $ Tools --> Programmer

Detect the JTAG chain

    $ Processing --> Auto Detect

Flash the QSPI device

This will take a few minutes to complete.

    $ Edit --> Change File. Select axe5000_top.jic
    $ Click the 'Program/Configure' check box.
    $ Processing --> Start

This will take up to a minute to complete.

Run the Demo

Open a terminal

     $ Open Tera-Term or equivalent terminal program
     $ set its baud rate to 115200
     $ Press the S1 button to configure the FPGA

Each time S2 is pressed, the readings are refreshed.

Build the Quartus Reference Design

This can be built under Windows or Linux.

Clone the repository. Open a shell (niosv command shell for Windows)

    $ git clone -b QPDS26.1_REL_GSRD_PR https://github.com/ArrowElectronics/refdes-agilex5 refdes-agilex5
    $ cd refdes-agilex5/axe5000/niosv_qspi_hyperram_refdes

Open Quartus and load the Project located in the folder shown above

    $ File --> Open Project. Select axe5000_top.qpf

Add pin assignments

    $ View --> Console
    $ In the Tcl Console window type 'source sources/axe5000_pin_assignment.tcl' and press Enter

Compile the Quartus project

    $ Processing --> Start Compilation

The following file is created:

  • agilex_5/refdes-agilex5/axe5000/accel_temp_refdes/axe5000_top.sof

Build the Software project

Use the steps detailed in chapter 5 of the Lab Guide for Lab 2 to build and/or debug the software project. The source code for this project is provided in the software/app directory. Section 5.3.1 does not need to be implemented.

In section 5.3.2.2 use the following command to create the software project.

    niosv-app --bsp_dir=software/bsp --app_dir=software/app -s=software/app/axe5000_demo_refdes.c

A script file has been provided with useful commands

Prerequisites

  • Review Getting Started
  • Host machine running Linux or Windows.
  • Internet connection to download the tools and clone the repositories from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
  • Quartus Prime Pro version 26.1 (with NIOS-V license)
  • Ashling RiscFree IDE for Intel FPGAs 26.1, if modifying software

Set up the Environment

Open a shell (niosv command shell for Windows)

    $ mkdir agilex_5
    $ cd agilex_5

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