Golden Hardware Reference Design - ArrowElectronics/Agilex-5 GitHub Wiki

Golden Hardware Reference Design

The Golden Hardware Reference Design (GHRD) for the AXE5-Eagle Development Platform provides a starter reference design. It includes a Platform Designer reference design that maps a number of HDL based FPGA peripherals to the HPS (Hard Processor System) and the ARM Cortex-76/Cortex-A55 processors. This design is intended as a starting point for new designs.

The user can either Create the Design from scratch or Use the Completed Design

Table of Contents

  1. Overview
  2. Create the Design
    1. Acquiring top-level files
    2. Creating project framework
    3. Create display sub-system
    4. Adding other Peripherals sub-system
    5. Creating Processor System
    6. Creating top-level design
  3. Use the Completed Design

Overview

The Golden Hardware Reference Design is an important part of the GSRD and consists of the following components:

  • ARM Cortex®-A76 and A55 HPS
  • HDMI Video output
  • Two user push-button inputs
  • Two user DIP switch inputs
  • Two user I/O for LED outputs
  • JTAG UART
  • System ID

MPU Address Maps

This section presents the address maps as seen from the MPU (A9) side.

Lightweight HPS-to-FPGA Address Map

The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is listed in the following table.

Periheral Address Offset Size (bytes) Attribute
sys_id 0x0100_0060 8 Unique system ID
pb 0x0100_0050 16 DIP switch input
dipsw 0x0100_0040 16 Push button input
rgb_led0 0x0100_0030 16 RGB LED0 output display
rgb_led1 0x0100_0020 16 RGB LED0 output display
rgb_led2 0x0100_0010 16 RGB LED0 output display
rgb_led3 0x0100_0000 16 RGB LED0 output display
onchip_sram 0x0000_0000 32K On-Chip SRAM
hdmi_dmac_0 0x0801_0000 2K HDMI DMA Controller
axi_hdmi_tx_0 0x0800_0000 64K HDMI Transmit IP

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface.

Periheral Interrupt Number Attribute
axi_dmac_0 fpga2hps_interrupt[0] Video DMA Controller
dipsw fpga2hps_interrupt[1] 2 DIP switch inputs (either edge)
jtag_uart fpga2hps_interrupt[2] JTAG UART
pd fpga2hps_interrupt[3] 2 push button (falling edge)

When Creating the Design, a full build should take between 25 to 60 minutes.

The build will produce the following items:

File Description
.sof SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
Handoff Folder containing a description of the hardware to be used by the Preloader Generator

Return - GSRD