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Table of Contents

Quick Start Guide
Build Instructions

Quick Start Guide

1. Introduction
2. Block Diagram
3. Install the Quartus Prime Pro Programmer
4. Configure the Board for the Demo
5. Program the FPGA configuration file.
6. Run the Demo

Introduction

This reference design implements a Nios V/m Microcontroller. The Nios® V/m Microcontroller is a soft core processor developed by Intel based on the RISC-V instruction set. A complete portfolio of Niov V processors is available, ranging from the Nios V/c Compact Microcontroller to the Nios V/g General Purpose Processor.

For more information on the suite of Nios V processor, click on the Nios V processor landing page.

Block Diagram

The reference design includes

• Nios V/m Microcontroller
• Onchip RAM
• JTAG UART
• System ID peripheral

Configure the Board for the Demo

The following components are required for the demo:

• AXE5000 (TEI0181) development board,
• USB C Cable

Assemble the Hardware

• Plug the USB Cable into J9, the USB C connector.

Program the FPGA configuration file

Open the Quartus Programmer

    $ Tools --> Programmer

Detect the JTAG chain

    $ Processing --> Auto Detect

Select the A5EC008BM16AE device in the topology diagram

Program the device

    $ Edit --> Change File. Select output_files/axe5000_top.sof
    $ Click the 'Program/Configure' check box.
    $ Processing --> Start

This will take a few seconds to complete.

Run the Demo

Launch the Nios V command shell

    $ Windows search --> Nios V.

Navigate to the project directory

    $ cd "agilex_5/refdes-agilex5/axe5000/first_niosv_refdes"  

Download the Nios V ELF file

     $ niosv-download -g -r -c 1 software/app/build/Debug/app.elf

Open a JTAG UART terminal

     $ juart-terminal

Build Instructions

Release Contents
Prerequisites
Build the Reference Design

Prerequisites

• Review Getting Started
• Host machine running Linux or Windows.
• Internet connection to download the tools and clone the repositories from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
• Quartus Prime Pro version 26.1 (with NIOS-V license)
• Ashling RiscFree IDE for Altera FPGAs 26.1

Build the Reference Design

Open a Nios V shell.

For Windows: Start --> Altera 26.1.xx Pro Edition --> Nios V Command Shell.

For Linux or WSL: Open a shell and then enter niosv-shell at the prompt.

Set up the Environment

Open a shell (niosv command shell for Windows)

    $ sudo rm -rf agilex_5
    $ mkdir agilex_5
    $ cd agilex_5
    $ export TOP_FOLDER=`pwd`

Build the Quartus Reference Design

This can be built under Windows or Linux.

Clone the repository. Open a shell (niosv command shell for Windows)

    $ git clone https://github.com/ArrowElectronics/refdes-agilex5
    $ cd refdes-agilex5/axe5000/first_niosv_refdes

Build the Software

Create the Boot Copier Application

Create the Boot Copier BSP

    niosv-bsp \
      ./software/bootcopier_bsp/settings.bsp \
      --create \
      --qsys=./top_system.qsys \
      --quartus-project=./axe5000_top.qpf \
      --type=hal \
      --cpu-instance=niosv_system_0_niosv_g \
      --script=./software/bootcopier_bsp/settings.tcl

Create the project

    niosv-app \
      -b=software/bootcopier_bsp \
      -a=software/bootcopier_app \
      -s=software/bootcopier_app/mailbox_bootloader.c

Create the project Makefile

    cmake \
      -G "Unix Makefiles" \
      -DCMAKE_BUILD_TYPE=Release \
      -B software/bootcopier_app/build/release \
      -S software/bootcopier_app

Build the project

    cmake \
      --build software/bootcopier_app/build/release

Create the OCM payload

    elf2hex software/bootcopier_app/build/release/bootcopier_app.elf \
      -b 0x1000000 \
      -w 32 \
      -e 0x100ffff \
      -o software/bootcopier_app/build/release/niosv_system_0_bootcopier_ocm.hex

Build the Hardware

Add pin assignments

    quartus_sh -t sources/axe5000_top.tcl

Compile the Quartus project

    quartus_sh --flow compile axe5000_top

The following file is created:

• agilex_5/refdes-agilex5/axe5000/niosv_qspi_hyperram_refdes/output_files/axe5000_top.sof

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