First Nios V Reference Design AXE5000 - ArrowElectronics/Agilex-5 GitHub Wiki

Introduction

This reference design implements a Nios V/m Microcontroller. The Nios® V/m Microcontroller is a soft core processor developed by Intel based on the RISC-V instruction set. A complete portfolio of Niov V processors is available, ranging from the Nios V/c Compact Microcontroller to the Nios V/g General Purpose Processor.

For more information on the suite of Nios V processor, click on the Nios V processor landing page.

Block Diagram

The reference design includes

• Nios V/m Microcontroller
• Onchip RAM
• JTAG UART
• System ID peripheral

Prerequisites

• Review Getting Started
• Host machine running Linux or Windows.
• Internet connection to download the tools and clone the repositories from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
• Quartus Prime Pro version 24.3

Set up the Environment

Open a shell (niosv command shell for Windows)

    $ mkdir axe5000
    $ cd axe5000

Build the Reference Design

This can be built under Windows or Linux.

Clone the repository. Open a shell (niosv command shell for Windows)

    $ cd axe5000
    $ git clone -b QPDS24.3_QPDS_REL_PR https://github.com/ArrowElectronics/refdes-agilex5 refdes-agilex5
    $ cd refdes-agilex5/axe5000/first_niosv_refdes

Open Quartus and load the Project located in the folder shown above

    $ File --> Open Project. Select axe5000_top.qpf

Add pin assignments

    $ View --> Tcl Console
    $ In the Tcl Console window type 'source sources/axe5000_pin_assignment' and press Enter

Compile the Quartus project

    $ Processing --> Start Compilation

The following file is created:

• axe5000/refdes-agilex5/axe5000/first_niosv_refdes/output_files/axe5000_top.sof

Configure the Board for the Demo

The following components are required for the demo:

• AXE5-Eagle (TEI0185) development board,
• 12VDC 40W power supply
• Arrow-USB-Blaster (TEI-0004-02) for downloading to the FPGA

Depending on the kit revision, additional components may need to be obtained. Please click on this link to review.

Assemble the Hardware

• Plug the Arrow-USB-Blaster (TEI0004-02) into J34 with the USB connector facing to the right.

• Connect the power supply to the AXE5-Eagle J29 barrel connector
• Plug the AC-DC adapter into an AC outlet

Program the FPGA configuration file

The FPGA JTAG chain will expose 1 or 2 endpoints when Auto Detected from the programmer. Follow the appropriate instructions to program the Agilex 5 FPGA for either scenario.

Open the Quartus Programmer

    $ Tools --> Programmer

Detect the JTAG chain

    $ Processing --> Auto Detect

Option 1: One Device

Option 2: Two Devices

Select the A5EC065BB32AE4SR0 device in the topology diagram

Program the device

    $ Edit --> Change File. Select output_files/axe5000_top.sof
    $ Click the 'Program/Configure' check box.
    $ Processing --> Start

This will take a few seconds to complete.

Run the demo

RGB_LED0 will begin cycling through Red --> Green --> Blue when the sof file has been downloaded. Press the FPGA_PB2 button to illuminate RGB_LED1 in green and the FPGA_PB3 button to illuminate RGB_LED1 in blue.