First Nios V Reference Design AXC3000 - ArrowElectronics/Agilex-5 GitHub Wiki
Introduction
This reference design implements a Nios V/m Microcontroller. The Nios® V/m Microcontroller is a soft core processor developed by Intel based on the RISC-V instruction set. A complete portfolio of Niov V processors is available, ranging from the Nios V/c Compact Microcontroller to the Nios V/g General Purpose Processor.
For more information on the suite of Nios V processor, click on the Nios V processor landing page.
Block Diagram
The reference design includes
- Nios V/m Microcontroller
- Onchip RAM
- JTAG UART
- System ID peripheral
Prerequisites
- Review Getting Started
- Host machine running Linux or Windows.
- Internet connection to download the tools and clone the repositories from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
- Quartus Prime Pro version 25.1
- Ashling RiscFree IDE for Intel FPGAs 25.1
Set up the Environment
Open a shell (niosv command shell for Windows)
$ mkdir agilex_3
$ cd agilex_3
Build the Quartus Reference Design
This can be built under Windows or Linux.
Clone the repository. Open a shell (niosv command shell for Windows)
$ cd axc3000
$ git clone -b QPDS25.1_QPDS_REL_PR https://github.com/ArrowElectronics/refdes-agilex3 refdes-agilex3
$ cd refdes-agilex3/axc3000/first_niosv_refdes
Open Quartus and load the Project located in the folder shown above
$ File --> Open Project. Select axc3000_top.qpf
Add pin assignments
$ View --> Console
$ In the Tcl Console window type 'source sources/axc3000_pin_assignment.tcl' and press Enter
Compile the Quartus project
$ Processing --> Start Compilation
The following file is created:
- agilex_3/refdes-agilex3/axc3000/first_niosv_refdes/output_files/axc3000_top.sof
Configure the Board for the Demo
The following components are required for the demo:
- AXC3000 (TEI0181) development board,
- USB C Cable
Assemble the Hardware
- Plug the USB Cable into J9, the USB C connector.
Program the FPGA configuration file
Open the Quartus Programmer
$ Tools --> Programmer
Detect the JTAG chain
$ Processing --> Auto Detect
Select the A3CY100BM16AE7S device in the topology diagram
Program the device
$ Edit --> Change File. Select output_files/axc3000_top.sof
$ Click the 'Program/Configure' check box.
$ Processing --> Start
This will take a few seconds to complete.
Run the Nios V software
Launch the Nios V command shell
$ Windows search --> Nios V.
Navigate to the project directory
$ cd "agilex_3/refdes-agilex3/axc3000/first_niosv_refdes"
Download the Nios V ELF file
$ niosv-download -g -r -c 1 software/app/build/Debug/app.elf
Open a JTAG UART terminal
$ juart-terminal