Quick Start Guide
Build Instructions
Configure the FPGA with a Device Tree Overlay
Release Notes

This Quick Start Guide describes the hardware and software setup needed to run the Yocto Linux Command-Line demo.

In this demo configuration, the Agilex® 5 E boots a Yocto Linux Distribution which uses a terminal emulator to communicate with the user.

To run the Yocto Linux Command-Line demo, follow the steps below:

1. Golden Hardware Reference Design (GHRD) Overview
2. Convert the Arrow Blaster to a USB-Blaster III
3. Install the Quartus Prime Pro Programmer
4. Prepare and install the SD Card.
5. Configure the Board for the Demo
6. Flash the FPGA configuration file.
7. Connect to the HPS target terminal.
8. Boot log
9. Access FPGA PIO from Linux
10. Access FPGA Peripherals and FPGA/HPS LPDDR4 Memory from the FPGA & the HPS

The Golden Hardware Reference Design is an important part of a bootable Linux system and consists of the following components:

• Hard Processor System (HPS)
  • Dual core Arm Cortex-A76 processor
  • Dual core Arm Cortex-A55 processor
  • HPS Peripherals:
    • SDMMC
    • EMAC
    • USB UART
    • I2C
    • USB 3.1 (2.0 mode)
• Multi-Ported FrontEnd(MPFE) for HPS External Memory Interface (EMIF)
• FPGA Peripherals connected to Lightweight HPS-to-FPGA (LWS2F) AXI Bridge and JTAG to Avalon Master Bridge
  • HDMI Video output
  • Two user push-button inputs
  • Two user DIP switch inputs
  • Four user I/O for RGB LED outputs
  • JTAG UART
  • System ID
• FPGA Peripherals connected to HPS-to-FPGA (S2F) AXI Bridge
  • FPGA External Memory Interface (EMIF)

The GHRD is constructed with hierarchy. There is a top level which instantiates multiple subsystems. These include the following subsystems:

• Board
• Clock
• HPS
• EMIF
• Peripheral
• Video

This section presents the address maps as seen from the MPU .

The three FPGA windows in the MPU address map provide access to 256 GB of FPGA space. First window is 1 GB from 00_4000_0000, second window is 15 GB from 04_4000_0000, third window is 240 GB from 44_0000_0000. The following table lists the offset of each peripheral from the HPS-to-FPGA bridge in the FPGA portion of the SoC.

The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0x00_2000_0000, is listed in the following table.

There are three JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGA fabric, and another for accessing SDRAM attached to the HPS through the FPGA-to-SDRAM Interface and another for FPGA fabric to SDRAM. The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface.

The following components are required for the demo:

• AXE5-Eagle (TEI0185) development board,
• 12VDC 40W power supply
• Arrow-USB-Blaster (TEI-0004-02) for downloading to the FPGA
• 2 x micro-USB Cable (one for the Arrow Blaster, one for the HPS UART)
• 8GB SD card

Depending on the kit revision, additional components may need to be obtained. Please click on this link to review.

The MSEL2 and MSEL1 DIP switches need to be set to the ON position (left) for Boot from QSPI configuration.

• Insert the SD card in the J24 cage, on the right hand of the board.

• Attach the micro-USB cable to UART (J5) connector

• Plug the Arrow-USB-Blaster (TEI0004-02) into J34 with the USB connector facing to the right.

• Connect the power supply to the AXE5-Eagle J29 barrel connector
• Plug the AC-DC adapter into an AC outlet

• Download the FPGA jic image axe5_eagle_top.hps.jic

The FPGA JTAG chain will expose 1 or 2 devices when auto-detected from the programmer. Follow the appropriate instructions to program the Agilex 5 FPGA for either scenario.

Open a shell (Nios V Command Shell for Windows)

Determine the number of JTAG devices

    $ jtagconfig

One JTAG device
1) USB-Blaster III [USB-1]
  0364F0DD   A5E(C065BB32AR0|D065BB32AR0)

Two JTAG devices
1) USB-Blaster III [USB-1]
  4BA06477   ARM_CORESIGHT_SOC_600
  0364F0DD   A5E(C065BB32AR0|D065BB32AR0)

Option 1: One Device

    $ quartus_pgm -c 1 -m jtag -o "pvi;axe5_eagle_top.hps.jic@1"

Option 2: Two Devices

    $ quartus_pgm -c 1 -m jtag -o "pvi;axe5_eagle_top.hps.jic@2"

Program the device

This will take a few minutes to complete.

• A wired Micro USB serial port connection between the host PC and the embedded target is required
• Launch a terminal program (like Tera Term VT or Putty) and connect using serial port
• Select 115200 baud
• Select the appropriate target COM port

Press the 'NCONFIG' button to boot the demo. This will initiate the following boot process.

• The Secure Device Manager (SDM) will read the jic file. This contains the FPGA EMIF I/O image and the U-boot First Stage Boot Loader (FSBL)
• When the FPGA is configured, the SDM will release the Arm processor cluster in the Hard Processing System (HPS) from reset.
• The Arm processor cluster then boots U-boot and configures the FPGA I/O and core. Then Linux boots from the SD card
• The Linux password is root

RGB_LED2 is connected to a PIO peripheral in the FPGA. This is mapped via the HPS2FPGA Lightweight Bridge (LW HPS2FPGA) to the HPS.RGB_LED2 has been added as an LED device in Linux. This was done with the following lines of code in the Device Tree

View the LEDs as devices

    $ ls /sys/class/leds

Illuminate RGB_LED2 - red

    $ echo 1 > /sys/class/leds/fpga_led2_red/brightness

Turn off RGB_LED2

    $ echo 0 > /sys/class/leds/fpga_led2_red/brightness

Reboot the linux system. Halt at the u-boot prompt

Reload the FPGA core image

    $ load mmc 0:1 ${loadaddr} ghrd.core.rbf;
    $ fpga load 0 ${loadaddr} ${filesize};
    $ bridge enable;

Open Quartus and then System Console

    $ Tools --> System Debugging Tools --> System Console

List all JTAG masters

    $ get_service_paths master

Select and open the fpga_only_master

    $ set fpga_only_master [lindex [get_service_paths master] 0]
    $ open_service master $fpga_only_master

Read the System ID peripheral

    $ master_read_32 $fpga_only_master 0x08000000 1

Read the Push Button PIO

    $ master_read_32 $fpga_only_master 0x08000010 1

Press FPGA_PB2 and read again

    $ master_read_32 $fpga_only_master 0x08000010 1

Read the DIP Switch PIO

    $ master_read_32 $fpga_only_master 0x08000020 1

Change the position of FPGA_SW3 and read again

    $ master_read_32 $fpga_only_master 0x08000020 1

Illuminate RGB_LED2 - red

    $ master_write_32 $fpga_only_master 0x08000050 0x03

Illuminate RGB_LED2 - green

    $ master_write_32 $fpga_only_master 0x08000050 0x05

Illuminate RGB_LED2 - blue

    $ master_write_32 $fpga_only_master 0x08000050 0x06

Turn off RGB_LED2

    $ master_write_32 $fpga_only_master 0x08000050 0x07

Select and open the fpga_emif_only_master

    $ set fpga_emif_only_master [lindex [get_service_paths master] 1]
    $ open_service master $fpga_emif_only_master

Write and read FPGA LPDDR4 memory

    $ master_read_32 $fpga_emif_only_master 0x00000000 1

    $ master_write_32 $fpga_emif_only_master 0x00000000 0x12345678

    $ master_read_32 $fpga_emif_only_master 0x00000000 1

Select and open the fpga_master

    select node 2 for f2h bridge transfers
    $ set f2h_f2s_master [lindex [get_service_paths master] 2]

    **OR**

    select node 3 for f2s bridge transfers
    $ set f2h_f2s_master [lindex [get_service_paths master] 3]

    $ open_service master $f2h_f2s_master

Write a test pattern (u-boot)

    $ mtest 0x84000000 0x84000100 0x12345600 1

Flush the data cache into DRAM (u-boot)

    $ dcache flush

Verify the data from HPS (u-boot)

    $ md.l 0x84000000 0x40

Verify the data from the FPGA (System Console)

    $ master_read_32 $f2h_f2s_master 0x84000000 0x040

Flush the data cache into DRAM (u-boot)

    $ dcache flush

Write data from the FPGA to HPS DRAM (System Console)

    $ master_write_32 $f2h_f2s_master 0x84000000 0x98765432

Verify the data from HPS (u-boot)

    $ md.l 0x84000000 1

Close the jtag master (System Console)

    $ close_service master $f2h_f2s_master

FPGA peripherals are connected to a local JTAG master and an LWH2F bridge for HPS master access.

RGB_LED2 is connected to a PIO peripheral in the FPGA. This is mapped to the HPS via the LWH2F Bridge. The LWH2F bridge has a base address of 0x2000 0000 within the HPS memory map. Its span is defined in Platform Designer. The PIO has a local address of 0x0800 0050.

The address of the PIO, accessible from the HPS, is 

0x2000 0000       LWH2F Bridge address 
+
0x0800 0050       PIO offset address in the FPGA
-----------
0x2800 0050

Turn on RGB_LED2 - red

    $ mw.l 0x28000050 0x03 (u-boot)

Turn on RGB_LED2 - green

    $ mw.l 0x28000050 0x05 (u-boot)

Turn on RGB_LED2 - blue

    $ mw.l 0x28000050 0x06 (u-boot)

Verify the data from the FPGA (System Console)

    $ master_read_32 $fpga_only_master 0x08000050 1

Turn off RGB_LED2

    $ mw.l 0x28000050 0x07 (u-boot)

A FPGA External Memory Interface (EMIF) is connected to a local JTAG EMIF master and an H2F bridge for HPS master access. This is mapped to the HPS via the H2F Bridge. The H2F bridge has a base address of 0x4000 0000 within the HPS memory map. Its span is defined in Platform Designer. The EMIF has a local address of 0x0000 0000. A one-gigabyte LPDDR4 device is connected to the EMIF controller in the FPGA.

Select and open the fpga_emif_only_master

    select node 1 for access to the FPGA EMIF Only JTAG master
    $ set fpga_emif_only_master [lindex [get_service_paths master] 1]

    $ open_service master $fpga_emif_only_master

Write a test pattern (u-boot)

    $ mtest 0x40000000 0x40000100 0x12345600 1

Verify the data from HPS (u-boot)

    $ md.l 0x40000000 0x40

Verify the data from the FPGA (System Console)

    $ master_read_32 $fpga_emif_only_master 0x00000000 0x040

Write data to the FPGA DRAM (System Console)

    $ master_write_32 $fpga_emif_only_master 0x00000000 0x98765432

Verify the data from HPS (u-boot)

    $ md.l 0x40000000 1

This build flow is derived from the instructions on the Building Bootloader for Agilex 5 page on RocketBoards

Release Contents
Prerequisites
Set up the Environment
Build the Golden Hardware Reference Design
Build Arm Trusted Firmware
Build u-boot
Build the Linux kernel
Download or Build the Yocto Rootfs
Create an Integrated SOF file
Create an Integrated JIC file
Build the SD Card Image
Downloading via JTAG

• Host machine running Linux (for Quartus, ATF, U-Boot, Linux & Yocto). Ubuntu 22.04 was used, but other versions may work too. For Quartus only, optionally, a Host Machine running Windows.
• Internet connection to download the tools and clone the repositories from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
• Quartus Prime Pro version 25.3

Open a shell

    $ sudo rm -rf agilex_5
    $ mkdir agilex_5
    $ cd agilex_5
    $ export TOP_FOLDER=`pwd`

Download and setup the the toolchain as follows:

    $ cd $TOP_FOLDER
    $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
    $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
    $ rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
    $ export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
    $ export ARCH=arm64
    $ export CROSS_COMPILE=aarch64-none-linux-gnu-

This can be built under Windows or Linux.

Open a shell (niosv command shell for Windows)

For Linux, specify the path to the Quartus installation

    $ export PATH="<path to >/altera_pro_pro/25.3/quartus/bin64:$PATH"

Clone the repository

    $ cd $TOP_FOLDER
    $ git clone -b QPDS25.3_REL_GSRD_PR https://github.com/ArrowElectronics/ghrd-socfpga ghrd-socfpga
    $ cd ghrd-socfpga/axe5_eagle_ghrd

Open Quartus and load the Project

    $ File --> Open Project. Select axe5_eagle_top.

Add pin assignments

    $ View --> Console
    $ In the Tcl Console window type 'source sources/axe5_eagle_pin_assignment.tcl' and press Enter

Compile the Quartus project

    $ Processing --> Start Compilation

The following file is created:

• $TOP_FOLDER/ghrd-socfpga/axe5_eagle_ghrd/output_files/axe5_eagle_top.sof

    $ cd $TOP_FOLDER
    $ rm -rf arm-trusted-firmware
    $ git clone -b QPDS25.3_REL_GSRD_PR https://github.com/ArrowElectronics/arm-trusted-firmware arm-trusted-firmware
    $ cd arm-trusted-firmware
    $ make -j 48 PLAT=agilex5 bl31 

The following file is created:

• $TOP_FOLDER/arm-trusted-firmware/build/agilex5/release/bl31.bin (used for u-boot.itb generation)

    $ cd $TOP_FOLDER 
    $ rm -rf u-boot-socfpga 
    $ git clone -b QPDS25.3_REL_GSRD_PR https://github.com/ArrowElectronics/u-boot-socfpga u-boot-socfpga 
    $ cd u-boot-socfpga

    enable dwarf4 debug info, for compatibility with arm ds
    $ sed -i 's/PLATFORM_CPPFLAGS += -D__ARM__/PLATFORM_CPPFLAGS += -D__ARM__ -gdwarf-4/g' arch/arm/config.mk

    only boot from SD, do not try QSPI and NAND
    $ sed -i 's/u-boot,spl-boot-order.*/u-boot\,spl-boot-order = \&mmc;/g' arch/arm/dts/socfpga_agilex5_axe5_eagle-u-boot.dtsi

    disable NAND in the device tree
    $ sed -i '/&nand {/!b;n;c\\tstatus = "disabled";' arch/arm/dts/socfpga_agilex5_axe5_eagle-u-boot.dtsi

    link to atf
    $ ln -s ../arm-trusted-firmware/build/agilex5/release/bl31.bin

    build U-Boot
    $ make clean && make mrproper
    $ make socfpga_agilex5_defconfig 

    use created custom configuration file to merge with the default configuration obtained in .config file. 
    $ ./scripts/kconfig/merge_config.sh -O . -m .config config-fragment-eagle
    $ make -j 64

The following files are created:

• $TOP_FOLDER/u-boot-socfpga/u-boot.itb
• $TOP_FOLDER/u-boot-socfpga/spl/u-boot-spl-dtb.hex

Download and compile Linux

    $ cd $TOP_FOLDER 
    $ rm -rf linux-socfpga
    $ git clone -b QPDS25.3_REL_GSRD_PR https://github.com/ArrowElectronics/linux-socfpga linux-socfpga 
    $ cd linux-socfpga

    add arrow dts folder as Makefile option 
    $ sed -i '$ a subdir-y += arrow' arch/arm64/boot/dts/Makefile

    $ make defconfig 
    use created custom configuration file to merge with the default configuration obtained in .config file.
    ./scripts/kconfig/merge_config.sh -O ./ ./.config ./config-fragment-eagle

    make oldconfig
    $ make -j 64 Image && make arrow/socfpga_agilex5_axe5_eagle.dtb 

The following files are created:

• $TOP_FOLDER/linux-socfpga/arch/arm64/boot/Image
• $TOP_FOLDER/linux-socfpga/arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_eagle.dtb

The rootfs has been built and can be downloaded from the links below. Download both files and place them in the following folder

• $TOP_FOLDER/yocto/build/tmp/deploy/images/agilex5/

core-image-minimal-agilex5.rootfs-20240513114121.tar.gz

core-image-minimal-agilex5.rootfs.tar.gz

Use these instructions on Rocketboards to build the Rootfs. This is useful if you'd like to customize packages included in the rootfs.

The following file is created:

• $TOP_FOLDER/yocto/build/tmp/deploy/images/agilex5/core-image-minimal-agilex5.rootfs.tar.gz

This section presents how to add the FSBL to the SOF file which is the output of the hardware project compilation. This creates a new SOF file which can be used to configure the device through the Quartus Programmer. This is useful during development, as it takes much less time than writing a configuration image to QSPI.

    $ export PATH="<path to >/altera_pro/25.3/quartus/bin:$PATH"
    $ cd $TOP_FOLDER/ghrd-socfpga/axe5_eagle_ghrd/output_files/
    $ quartus_pfg -c axe5_eagle_top.sof  axe5_eagle_top_hps.sof -o hps_path=$TOP_FOLDER/u-boot-socfpga/spl/u-boot-spl-dtb.hex

    $ open a Nios V Command Shell
    $ cd <path to>/ghrd-socfpga/axe5_eagle_ghrd/output_files/
    $ copy u-boot-spl.ihex from the linux host to the output_files directory
    $ quartus_pfg -c axe5_eagle_top.sof  axe5_eagle_top_hps.sof -o hps_path=u-boot-spl-dtb.hex

This section shows how to take the integrated sof file and create a jic file that can be programmed into the SDM QSPI flash. Note that downloading a sof file will not support the functionality of the linux reboot command or the HPS COLD RESET due to SDM requirements. It is useful to flash the QSPI when these functions are necessary.

    $ export PATH="<path to >/altera_pro/25.3/quartus/bin64:$PATH"        
    $ cd $TOP_FOLDER/ghrd-socfpga/axe5_eagle_ghrd/output_files/
    $ quartus_pfg -c axe5_eagle_top.sof axe5_eagle_top.jic -o hps=on -o device=MT25QU02G -o flash_loader=A5ED065BB32AE5SR0 -o hps_path=$TOP_FOLDER/u-boot-socfpga/spl/u-boot-spl-dtb.hex -o mode=ASX4

    $ open a Nios V Command Shell
    $ cd <path to>/ghrd-socfpga/axe5_eagle_ghrd/output_files/
    $ copy u-boot-spl.ihex from linux host to the output_files directory
    $ quartus_pfg -c axe5_eagle_top.sof axe5_eagle_top.jic -o hps=on -o device=MT25QU02G -o flash_loader=A5ED065BB32AE5SR0 -o hps_path=u-boot-spl-dtb.hex -o mode=ASX4

The following files are created:

• $TOP_FOLDER/ghrd-socfpga/axe5_eagle_ghrd/output_files/axe5_eagle_top.hps.jic
• $TOP_FOLDER/ghrd-socfpga/axe5_eagle_ghrd/output_files/axe5_eagle_top.core.rbf (rename it to ghrd.core.rbf)

The Agilex™ 5 device has two JTAG device IDs for the ARM SoC and FPGA respectively. The Secure Device Manager will determine whether to expose one or both.

Determine the number of JTAG devices.

    $ jtagconfig

Two devices:

1) USB Blaster III [USB-1]
  4BA06477   ARM_CORESIGHT_SOC_600
  0364F0DD   A5E(C065BB32AR0|D065BB32AR0)

One device:

1) USB Blaster III [USB-1]
  0364F0DD   A5E(C065BB32AR0|D065BB32AR0)

Substitute @n below with @1 for one device and @2 for two devices.

Download the sof.

    $ quartus_pgm -c 1 -m jtag -o "p;axe5_eagle_top_hps.sof@n"

Flash the QSPI.

    $ quartus_pgm -c 1 -m jtag -o "pvi;axe5_eagle_top.hps.jic@n"

Determine the device associated with the SD card on the host. Run the command below before and after inserting the SD card. The new drive letter will show up as /dev/sdx/ where x represents the actual letter (a,b,c,d etc). Substitute the letter x with the actual letter in the dd commands listed below.

    $ cat /proc/partitions

    $ cd $TOP_FOLDER
    $ sudo rm -rf sd_card && mkdir sd_card && cd sd_card
    $ wget https://releases.rocketboards.org/release/2020.11/gsrd/tools/make_sdimage_p3.py
    $ # remove mkfs.fat parameter which has some issues on Ubuntu 22.04
    $ sed -i 's/\"\-F 32\",//g' make_sdimage_p3.py
    $ chmod +x make_sdimage_p3.py
    $ mkdir fatfs &&  cd fatfs
    $ cp $TOP_FOLDER/ghrd-socfpga/axe5_eagle_ghrd/output_files/ghrd.core.rbf .
    $ cp $TOP_FOLDER/u-boot-socfpga/u-boot.itb .
    $ cp $TOP_FOLDER/linux-socfpga/arch/arm64/boot/Image .
    $ cp $TOP_FOLDER/linux-socfpga/arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_eagle.dtb .
    $ cd ..
    $ mkdir rootfs && cd rootfs
    $ sudo tar xf $TOP_FOLDER/yocto/build/tmp/deploy/images/agilex5/core-image-minimal-agilex5.rootfs.tar.gz
    $ cd ..
    $ sudo python3 make_sdimage_p3.py -f \
      -P fatfs/*,num=1,format=fat32,size=512M \
      -P rootfs/*,num=2,format=ext3,size=512M \
      -s 1024M \
      -n sdcard.img
    $ sudo chmod 777 sdcard.img
    $ cd ..

Use dd utility to write the SD image to the SD card. Substitute the letter x with the actual drive letter discovered above.

    $ sudo dd if=$TOP_FOLDER/sd_card/sdcard.img of=/dev/sdx bs=1M status=progress

Flush the changes to the SD card.

    $ sudo sync

    $ cd $TOP_FOLDER/u-boot-socfpga

    comment out default bootcommand
    $ sed -i 's|CONFIG_BOOTCOMMAND=|# &|' config-fragment-eagle

    add new bootcommand. no reference to fpga peripherals
    $ echo 'CONFIG_BOOTCOMMAND="mmc rescan; mw.l 10d13224 14; mw.l 10d13228 14; mw.l 10d1323c 14; mw.l 10d13234 14; mw.l 10d13248 14;
      mw.l 10d1324C 14; mw.l 0x10D11028 0x01027fb0 1; mw.l 0x10c03304 0x410 1; mw.l 0x10c03300 0x00000410; mw.l 0x10c03300 0x00000000;
      mw.l 0x10c03300 0x00000410; fatload mmc 0:1 82000000 Image;fatload mmc 0:1 86000000 socfpga_agilex5_axe5_eagle.dtb;
      setenv bootargs console=ttyS0,115200 root=\${mmcroot} rw rootwait;booti 0x82000000 - 0x86000000"' >> config-fragment-eagle

    build U-Boot
    $ make clean && make mrproper
    $ make socfpga_agilex5_defconfig 

    use created custom configuration file to merge with the default configuration obtained in .config file. 
    $ ./scripts/kconfig/merge_config.sh -O . -m .config config-fragment-eagle
    $ make -j 64

    $ cd $TOP_FOLDER/linux-socfpga

    omit the ghrd devicetree
    $ sed -i 's|#include "socfpga_agilex_ghrd.dtsi"|// &|' arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_eagle.dts

    disable the emac routed through the fpga
    $ sed -i '/&gmac0 {/,/}/{s/status = "okay"/status = "disabled"/}' arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_eagle.dts

    modify the defconfig to support overlays
    $ make defconfig 

    use created custom configuration file to merge with the default configuration obtained in .config file.
    $ ./scripts/kconfig/merge_config.sh -O ./ ./.config ./config-fragment-eagle-overlay

    $ make -j 64 Image && make arrow/socfpga_agilex5_axe5_eagle.dtb && make arrow/overlay.dtb

    create the /lib/firmware directory on the linux partition of the SD card

    copy the following files to the /lib/firmware directory on the linux partition of the SD card
    $ ghrd.core.rbf
    $ overlay.dtb

    copy the updated u-boot file to the FAT partition of the SD card
    $ u-boot.itb

    copy the updated linux files to the FAT partition of the SD card
    $ Image
    $ sopcfpga_agilex5_axe5_eagle.dtb
    $ overlay.dtb

    load the overlay
    $ mkdir /sys/kernel/config/device-tree/overlays/0
    $ cd /lib/firmware/
    $ echo overlay.dtb > /sys/kernel/config/device-tree/overlays/0/path

    access the fpga led
    $ devmem2 0x28000030 w 0x06

    access the system id peripheral
    $ devmem2 0x28000000 w

1. Quick Start
   1. Added "Convert Arrow Blaster to USB-Blaster III" section
2. Linux build flow modified.
   1. add support for NTFS and FAT file systems
3. HPS EMAC0 enabled. To enable in linux, edit /etc/network/interfaces and reboot to utilize.
   1. edit line 17 to read, auto eth1
4. Ethernet now supported from U-boot on HPS EMAC2

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