AXE5 GoldenEagle connector pinout - ArrowElectronics/Agilex-5 GitHub Wiki
AXE5-GoldenEagle Connector Pin Assignments
This page lists signal pins on expansion connectors. non-signal pins are not mentioned. For full connector pinout, consult the schematics and/or User Guide.
FMC+ Connector
The FMC+ is a High Serial Pin Connector (HSPC) with 560 pins arranged in a 14x40 array. Only the colored signal boxes listed in the diagram below are connected to the Agilex 5.
A mezzanine board with an FMC HSPC (red region) can be used if the user doesn't need the signals in column L.
The connector image and a tabular pin assignment are shown below:
FMC+ (J3) Pinout
Note: The LA00-LA33 pins are connected to an HSIO bank on the Agilex-5. This bank can only be powered by a 1.2V or 1.3V power source. If using the LA00-LA33 pins as differential pairs, the VCCIO must be set to 1.3V via a DIP switch S10. For 1.3V, The FMC_ADJ DIP switch should be in the ON position as shown below.
| FMC+ Pin | FPGA Ball | Signal Name | VCCIO |
|---|---|---|---|
| A2 | GTSR4B_RX_CH1P (BD1) | DP1_M2C_P | CML |
| A3 | GTSR4B_RX_CH1N (BD3) | DP1_M2C_N | CML |
| A6 | GTSR4B_RX_CH2P (BB1) | DP2_M2C_P | CML |
| A7 | GTSR4B_RX_CH2N (BB3) | DP2_M2C_N | CML |
| A10 | GTSR4B_RX_CH3P (AY1) | DP3_M2C_P | CML |
| A11 | GTSR4B_RX_CH3N (AY3) | DP3_M2C_N | CML |
| A14 | GTSR4C_RX_CH0P (AV1) | DP4_M2C_P | CML |
| A15 | GTSR4C_RX_CH0N (AV3) | DP4_M2C_N | CML |
| A18 | GTSR4C_RX_CH1P (AT1) | DP5_M2C_P | CML |
| A19 | GTSR4C_RX_CH1N (AT3) | DP5_M2C_N | CML |
| A22 | GTSR4B_TX_CH1P (BC7) | DP1_C2M_P | CML |
| A23 | GTSR4B_TX_CH1N (BC10) | DP1_C2M_N | CML |
| A26 | GTSR4B_TX_CH2P (BA7) | DP2_C2M_P | CML |
| A27 | GTSR4B_TX_CH2N (BA10) | DP2_C2M_N | CML |
| A30 | GTSR4B_TX_CH3P (AW7) | DP3_C2M_P | CML |
| A31 | GTSR4B_TX_CH3N (AW10) | DP3_C2M_N | CML |
| A34 | GTSR4C_TX_CH0P (AU7) | DP4_C2M_P | CML |
| A35 | GTSR4C_TX_CH0N (AU10) | DP4_C2M_N | CML |
| A38 | GTSR4C_TX_CH1P (AR7) | DP5_C2M_P | CML |
| A39 | GTSR4C_TX_CH1N (AR10) | DP5_C2M_N | CML |
| FMC+ Pin | FPGA Ball | Signal Name | VCCIO |
|---|---|---|---|
| B12 | GTSR4C_RX_CH3P (AM1) | DP7_M2C_P | CML |
| B13 | GTSR4C_RX_CH3N (AM3) | DP7_M2C_N | CML |
| B16 | GTSR4C_RX_CH2P (AP1) | DP6_M2C_P | CML |
| B17 | GTSR4C_RX_CH2N (AP3) | DP6_M2C_N | CML |
| B20 | REFCLK_GTSR4C_CH1P (AP16) | GBTCLK1_M2C_P | CML |
| B21 | REFCLK_GTSR4C_CH1N (AP21) | GBTCLK1_M2C_N | CML |
| B32 | GTSR4C_TX_CH3P (AL7) | DP7_C2M_P | CML |
| B33 | GTSR4C_TX_CH3N (AL10) | DP7_C2M_N | CML |
| B36 | GTSR4C_TX_CH2P (AN7) | DP6_C2M_P | CML |
| B37 | GTSR4C_TX_CH2N (AN10) | DP6_C2M_N | CML |
| FMC+ Pin | FPGA Ball | Signal Name | VCCIO |
|---|---|---|---|
| C2 | GTSR4B_TX_CH0P (BE7) | DP0_C2M_P | CML |
| C3 | GTSR4B_TX_CH0N (BE10) | DP0_C2M_N | CML |
| C6 | GTSR4B_RX_CH0P (BF1) | DP0_M2C_P | CML |
| C7 | GTSR4B_RX_CH0N (BF3) | DP0_M2C_N | CML |
| C10 | CK8 | LA06_P | FMC_ADJ* |
| C11 | CL6 | LA06_N | FMC_ADJ* |
| C14 | CL20 | LA10_P | FMC_ADJ* |
| C15 | CK20 | LA10_N | FMC_ADJ* |
| C18 | BE46 | LA14_P | FMC_ADJ* |
| C19 | BF46 | LA14_N | FMC_ADJ* |
| C22 | BK49 | LA18_P | FMC_ADJ* |
| C23 | BM49 | LA18_N | FMC_ADJ* |
| C26 | CC52 | LA27_P | FMC_ADJ* |
| C27 | CA52 | LA27_N | FMC_ADJ* |
| C30 | FMC_SCL | 3.3V | |
| C31 | FMC_SDA | 3.3V |
* FMC_ADJ Voltage : 1.2V/1.3V depending on SEL_FMC_ADJ setting of S10D (pin4-5) . S10B OFF = 1.2V, S7B ON = 1.3V
| FMC+ Pin | FPGA Ball | Signal Name | VCCIO |
|---|---|---|---|
| D1 | PG_GROUP3 (3.3V rail) | PG_C2M | |
| D4 | REFCLK_GTSR4B_CH1P (AV16) | GBTCLK0_M2C_P | CML |
| D5 | REFCLK_GTSR4B_CH1N (AV21) | GBTCLK0_M2C_N | CML |
| D8 | CF22 | LA01_P | FMC_ADJ* |
| D9 | CH22 | LA01_N | FMC_ADJ* |
| D11 | CH31 | LA05_P | FMC_ADJ* |
| D12 | CF31 | LA05_N | FMC_ADJ* |
| D14 | CK17 | LA09_P | FMC_ADJ* |
| D15 | CL17 | LA09_N | FMC_ADJ* |
| D17 | BF57 | LA13_P | FMC_ADJ* |
| D18 | BF53 | LA13_N | FMC_ADJ* |
| D20 | BR41 | LA17_P | FMC_ADJ* |
| D21 | BU41 | LA17_N | FMC_ADJ* |
| D23 | BW49 | LA23_P | FMC_ADJ* |
| D24 | CA49 | LA23_N | FMC_ADJ* |
| D26 | BM52 | LA26_P | FMC_ADJ* |
| D27 | BP52 | LA26_N | FMC_ADJ* |
| D34 | GND | FMC_TRST_L |
* FMC_ADJ Voltage : 1.2V/1.3V depending on SEL_FMC_ADJ setting of S10D (pin4-5) . S10B OFF = 1.2V, S7B ON = 1.3V
| FMC+ Pin | FPGA Ball | Signal Name | VCCIO |
|---|---|---|---|
| G2 | REFCLK_GTSR4C_RX_P (AT16) | FMC_CK1_M2C_P | CML |
| G3 | REFCLK_GTSR4C_RX_N (AT21) | FMC_CK1_M2C_N | CML |
| G6 | CF19 | LA00_P | FMC_ADJ* |
| G7 | CC19 | LA00_N | FMC_ADJ* |
| G9 | CC28 | LA03_P | FMC_ADJ* |
| G10 | CF28 | LA03_N | FMC_ADJ* |
| G12 | CL14 | LA08_P | FMC_ADJ* |
| G13 | CL11 | LA08_N | FMC_ADJ* |
| G15 | BH38 | LA12_P | FMC_ADJ* |
| G16 | BH41 | LA12_N | FMC_ADJ* |
| G18 | BF50 | LA16_P | FMC_ADJ* |
| G19 | BE50 | LA16_N | FMC_ADJ* |
| G21 | CA38 | LA20_P | FMC_ADJ* |
| G22 | BW38 | LA20_N | FMC_ADJ* |
| G24 | CF49 | LA22_P | FMC_ADJ* |
| G25 | CH49 | LA22_N | FMC_ADJ* |
| G27 | CL51 | LA25_P | FMC_ADJ* |
| G28 | CK54 | LA25_N | FMC_ADJ* |
| G30 | CK33 | LA29_P | FMC_ADJ* |
| G31 | CL30 | LA29_N | FMC_ADJ* |
| G33 | CK39 | LA31_P | FMC_ADJ* |
| G34 | CL39 | LA31_N | FMC_ADJ* |
| G36 | CL42 | LA33_P | FMC_ADJ* |
| G37 | CK45 | LA33_N | FMC_ADJ* |
* FMC_ADJ Voltage : 1.2V/1.3V depending on SEL_FMC_ADJ setting of S10D (pin4-5) . S10B OFF = 1.2V, S7B ON = 1.3V
| FMC+ Pin | FPGA Ball | Signal Name | VCCIO |
|---|---|---|---|
| H4 | REFCLK_GTSR4B_RX_P (AY16) | FMC_CK0_M2C_P | CML |
| H5 | REFCLK_GTSR4B_RX_N (AY21) | FMC_CK0_M2C_N | CML |
| H7 | CC22 | LA02_P | FMC_ADJ* |
| H8 | CA22 | LA02_N | FMC_ADJ* |
| H10 | CA31 | LA04_P | FMC_ADJ* |
| H11 | CC31 | LA04_N | FMC_ADJ* |
| H13 | CK11 | LA07_P | FMC_ADJ* |
| H14 | CL8 | LA07_N | FMC_ADJ* |
| H16 | CL23 | LA11_P | FMC_ADJ* |
| H17 | CK26 | LA11_N | FMC_ADJ* |
| H19 | BE64 | LA15_P | FMC_ADJ* |
| H20 | BF64 | LA15_N | FMC_ADJ* |
| H22 | CK66 | LA19_P | FMC_ADJ* |
| H23 | CL70 | LA19_N | FMC_ADJ* |
| H25 | BR38 | LA21_P | FMC_ADJ* |
| H26 | BU38 | LA21_N | FMC_ADJ* |
| H28 | CF52 | LA24_P | FMC_ADJ* |
| H29 | CH52 | LA24_N | FMC_ADJ* |
| H31 | BP41 | LA28_P | FMC_ADJ* |
| H32 | BM41 | LA28_N | FMC_ADJ* |
| H34 | CK35 | LA30_P | FMC_ADJ* |
| H35 | CL35 | LA30_N | FMC_ADJ* |
| H37 | CK48 | LA32_P | FMC_ADJ* |
| H38 | CL45 | LA32_N | FMC_ADJ* |
* FMC_ADJ Voltage : 1.2V/1.3V depending on SEL_FMC_ADJ setting of S10D (pin4-5) . S10B OFF = 1.2V, S7B ON = 1.3V
| FMC+ Pin | FPGA Ball | Signal Name | VCCIO |
|---|---|---|---|
| L16 | FMC_SYNC_C2M_P (CH41) | SYNC_C2M_P | FMC_ADJ* |
| L17 | FMC_SYNC_C2M_N (CF41) | SYNC_C2M_N | FMC_ADJ* |
| L20 | FMC_REFCK_C2M_P (BE61) | REFCLK_C2M_P | FMC_ADJ* |
| L21 | FMC_REFCK_C2M_N (BE57) | REFCLK_C2M_N | FMC_ADJ* |
| L24 | FMC_REFCK_M2C_P (CH38) | REFCLK_M2C_P | FMC_ADJ* |
| L25 | FMC_REFCK_M2C_N (CF38) | REFCLK_M2C_N | FMC_ADJ* |
| L28 | FMC_SYNC_M2C_P (BH49) | SYNC_M2C_P | FMC_ADJ* |
| L29 | FMC_SYNC_M2C_N (BH52) | SYNC_M2C_N | FMC_ADJ* |
| FMC+ Pin | FPGA Ball | Signal Name | VCCIO |
|---|---|---|---|
| Z1 | 3.3V pullup | PRSNT_M2C_L |
SFP+ Connector
There are 2x SFP+ connectors on the AXE5-GoldenEagle board and they are both connected to the same IO bank on the SoC FPGA. However, an HSIO bank can support only 1x 10Gb Ethernet Hard IP per bank. This means that if the user needs to use both 10Gb Ethernet ports, one will have to use a Soft IP.
Note: The SFP Control pins are connected to an HSIO banks on the Agilex-5. These bank can only be powered by a 1.2V or 1.3V power source. The Bank VCCIO must be set to either 1.2V or 1.3V via a DIP switch S10. For 1.3V, The CRUVI_VADJ_T or CRUVI_VADJ_B DIP switch should be in the ON (closed) position as shown below.
The SFP+ control signals go through a 1.2V to 3.3V level translator between the SoC FPGA and the connector. Similarly, the MUX_I2C signals go through a 1.8V to 3.3V level translation through the I2C MUX.
| SFPA Signal | FPGA Ball | VCCIO |
|---|---|---|
| SFPA_TX_DIS | Y77 | VIO_CRUVI_B |
| SFPA_TX_FAULT | Y74 | VIO_CRUVI_B |
| SFPA_RS1 | AG83 | VIO_CRUVI_B |
| SFPA_RS0 | B73 | VIO_CRUVI_B |
| SFPA_LOS | A76 | VIO_CRUVI_B |
| SFPA_M-DEF0 | A80 | VIO_CRUVI_B |
| SFPA_SDA* | MUX_I2C_SDA (F4) | 1.8V |
| SFPA_SCL* | MUX_I2C_SCL (D4) | 1.8V |
| SFPA_TD_P | GTSL1A_TX_CH3P (BG129) | |
| SFPA_TD_N | GTSL1A_TX_CH3N (BG126) | |
| SFPA_RD_P | GTSL1A_RX_CH3P (BF135) | |
| SFPA_RD_N | GTSL1A_RX_CH3N (BF133) |
| SFPB Signal | FPGA Ball | VCCIO |
|---|---|---|
| SFPB_TX_DIS | AC50 | VIO_CRUVI_T |
| SFPB_TX_FAULT | AG61 | VIO_CRUVI_T |
| SFPB_RS1 | AC53 | VIO_CRUVI_T |
| SFPB_RS0 | A66 | VIO_CRUVI_B |
| SFPB_LOS | A85 | VIO_CRUVI_B |
| SFPB_M-DEF0 | Y58 | VIO_CRUVI_T |
| SFPB_SDA* | MUX_I2C_SDA (F4) | 1.8V |
| SFPB_SCL* | MUX_I2C_SCL (D4) | 1.8V |
| SFPB_TD_P | GTSL1C_TX_CH3P (AL129) | |
| SFPB_TD_N | GTSL1C_TX_CH3N (AL126) | |
| SFPB_RD_P | GTSL1C_RX_CH3P (AK135) | |
| SFPB_RD_N | GTSL1C_RX_CH3N (AK133) |
*Note: The user must set up the TCA9544A I2C MUX to select the appropriate SFP+ port to communicate with.
HDMI Output
The HDMI connector (J11) is driven by a Texas Instruments TFP410 HDMI Transmitter device. The TFP410is driven from the SoC FPGA with a parallel 24-bit bus and control signals described in the table below. All signals are driven from HVIO banks powered at 1.8V.
The HDMI I2C signals are driven by the I2C MUX (see TCA9544A above).
| HDMI Signal | FPGA Ball |
|---|---|
| HDMI_I2C_SCL | MUX_I2C_SCL (D4) |
| HDMI_I2C_SDA | MUX_I2C_SDA (F4) |
| SDA_A | CF9 |
| SCL_A | BW19 |
| HDMI_CLK | BK31 |
| HDMI_HS | CF12 |
| HDMI_VS | BH19 |
| HDMI_DE | BK19 |
| HDMI_D0 | BF32 |
| HDMI_D1 | CH12 |
| HDMI_D2 | BM22 |
| HDMI_D3 | BF21 |
| HDMI_D4 | BE21 |
| HDMI_D5 | BP22 |
| HDMI_D6 | BR22 |
| HDMI_D7 | BE25 |
| HDMI_D8 | BU22 |
| HDMI_D9 | BW28 |
| HDMI_D10 | BU28 |
| HDMI_D11 | BM31 |
| HDMI_D12 | BR28 |
| HDMI_D13 | BM28 |
| HDMI_D14 | BK28 |
| HDMI_D15 | BH28 |
| HDMI_D16 | BF36 |
| HDMI_D17 | BE43 |
| HDMI_D18 | BU31 |
| HDMI_D19 | BP31 |
| HDMI_D20 | BR31 |
| HDMI_D21 | BF29 |
| HDMI_D22 | BF40 |
| HDMI_D23 | BE29 |
RJ-45 Connectors (J4 and J28)
There are 2 RJ-45 Ethernet connectors on the AXE5-GoldenEagle board which are driven by ADIN1300 Ethernet PHY devices. Each of the PHY devices is driven by the RGMII signals described below.
The RJ45 (J4) is driven from the HPS EMAC2 connected to the HPS MUX and driven at 1.8V logic levels.
| Signal Name | FPGA Ball |
|---|---|
| ETH_RST | T124 |
| ETH_MDC | Y132 |
| ETH_MDIO | T127 |
| ETH_TXCK | M127 |
| ETH_TXCTL | K127 |
| ETH_RXCK | M124 |
| ETH_RXCTL | AB127 |
| ETH_TXD0 | K124 |
| ETH_TXD1 | Y127 |
| ETH_TXD2 | F127 |
| ETH_TXD3 | Y124 |
| ETH_RXD0 | H127 |
| ETH_RXD1 | AB124 |
| ETH_RXD2 | F124 |
| ETH_RXD3 | D124 |
The RJ45 (J28) is driven from the FPGA Fabric with HVIO powered by a 1.8V voltage source. This can be driven by HPS EMAC0 (through the FPGA fabric) or by an Ethernet Triple Speed Ethernet (TSE) IP in the FPGA.
The interface to the HPS EMAC0 requires that the ETH1_RXCK and ETH1_RXD1 pins are swapped. This is implemented in the AXE5-GoldenEagle-ES release. HPS EMAC0 functionality will not be available with the AXE5-GoldenEagle-ES0 release.
| Signal Name | FPGA Ball |
|---|---|
| ETH1_RST | C2 |
| ETH1_MDC | G1 |
| ETH1_MDIO | J1 |
| ETH1_TXCK | D8 |
| ETH1_TXCTL | K8 |
| ETH1_RXCK | F8 |
| ETH1_RXCTL | H8 |
| ETH1_TXD0 | F27 |
| ETH1_TXD1 | F24 |
| ETH1_TXD2 | H22 |
| ETH1_TXD3 | D24 |
| ETH1_RXD0 | H18 |
| ETH1_RXD1 | D15 |
| ETH1_RXD2 | F18 |
| ETH1_RXD3 | F15 |
SD Card Connector (J24)
The SD Card interface comes from the HPS MUX pins which are powered by a 1.8V rail. The SD_DETECT is implemented using a GPIO. All pins, except SD_VSEL_1V8, go through a level translator between the SoC FPGA 1.8V rail to the connector's selectable 3.3V/1.8V rail.
| Signal Name | FPGA Ball | Function |
|---|---|---|
| SD_CLK | D132 | SD Clock |
| SD_CMD | AB132 | SD Command |
| SD_DAT0 | E135 | SD DATA 0 |
| SD_DAT1 | F132 | SD DATA 1 |
| SD_DAT2 | AA135 | SD DATA 2 |
| SD_DAT3 | V127 | SD DATA 3 |
| SD_VSEL_1V8 | P124 | HPS GPIO1_IO10, 0 -> SDIO_VCCB=3.3V, 1 -> SDIO_VCCB=1.8V |
PCIex4 Edge Connector (J1)
The PCIe on the AXE5-GoldenEagle is implemented as x4 Gen4 endpoint. The Agilex-5 is capable of supporting root port as well. The transceivers driving the data bus are powered by a 1.0V rail.
There is a differential 100MHz signal provided to the SoC FPGA related to the IP needs.
| Signal Name | FPGA Ball | Signal Type |
|---|---|---|
| PCIE_100M_CK_P | AY120 | Clock Generator(1.8V) |
| PCIE_100M_CK_N | AY115 | Clock Generator (1.8V) |
J1 Edge Connector:
| Signal Name | FPGA Ball | Signal Type |
|---|---|---|
| PCIE_RSTb | CF132 | GPIO (3.3V) |
| PCIE_R_WAKE | D34 | GPIO (3.3V) |
| PCIE_CLK_P | AV120 | J1 |
| PCIE_CLK_N | AV115 | J1 |
| PET0_P | GTSL1B_RX_CH0P (BD135) | J1 |
| PET0_N | GTSL1B_RX_CH0N (BD133) | J1 |
| PET1_P | GTSL1B_RX_CH1P (BB135) | J1 |
| PET1_N | GTSL1B_RX_CH1N (BB133) | J1 |
| PET2_P | GTSL1B_RX_CH2N (AY135)* | J1 |
| PET2_N | GTSL1B_RX_CH2P (AY133)* | J1 |
| PET3_P | GTSL1B_RX_CH3P (AV135) | J1 |
| PET3_N | GTSL1B_RX_CH3N (AV133) | J1 |
| PER0_P | GTSL1B_TX_CH0P (BE129) | J1 |
| PER0_N | GTSL1B_TX_CH0N (BE126) | J1 |
| PER1_P | GTSL1B_TX_CH1P (BC129) | J1 |
| PER1_N | GTSL1B_TX_CH1N (BC126) | J1 |
| PER2_P | GTSL1B_TX_CH2P (BA129) | J1 |
| PER2_N | GTSL1B_TX_CH2N (BA126) | J1 |
| PER3_P | GTSL1B_TX_CH3P (AW129) | J1 |
| PER3_N | GTSL1B_TX_CH3N (AW126) | J1 |
* Must be assigned this way for Quartus to pass. The PCIe takes care of the reversal
USB Type-A
The Quad-USB Type A connectors are driven from a Microchip 4-port USB HUB (USB5734T). This HUB interfaces to the SoC FPGA via USB ULP PHY (USB3320C) and a PIPE3 interfaces.
The ULPI signals are connected to the HPS MUX and the PIPE3 is connected to transceiver L1C_CH1
USB interface signals:
| Signal Name | FPGA Ball |
|---|---|
| USB_STP | L135 |
| USB_NXT | AD134 |
| USB_DIR | J135 |
| USB_CLK | P132 |
| USB_RST | B134 |
| USB_DATA0 | AD135 |
| USB_DATA1 | M132 |
| USB_DATA2 | K132 |
| USB_DATA3 | AG129 |
| USB_DATA4 | J134 |
| USB_DATA5 | AG120 |
| USB_DATA6 | G134 |
| USB_DATA7 | G135 |
| USB_SSTX_P | GTSL1C_TX_CH2P (AN129) |
| USB_SSTX_N | GTSL1C_TX_CH2N (AN126) |
| USB_SSRX_P | GTSL1C_RX_CH2P (AM135) |
| USB_SSRX_N | GTSL1C_RX_CH2N (AM133) |
USB-C (UART) Connector (J5)
The USB-C connector (J5) provides two UART COM ports into the FPGA fabric and HPS via the FTDI UB3 Blaster. These pins are connected to a 1.8V bank.
| Signal Name | FPGA Ball | Function |
|---|---|---|
| DBG_TXD | G2 | FPGA UART TXD |
| DBG_RXD | J2 | FPGA UART RXD |
| UART0_TXD | W134 | HPS UART TXD |
| UART0_RXD | AK115 | HPS UART RXD |
PMOD Connector (J17)
| Signal Name | FPGA Ball | VCCIO |
|---|---|---|
| P0_IO1 | BE115 | 3.3V |
| P0_IO2 | BF111 | 3.3V |
| P0_IO3 | BF107 | 3.3V |
| P0_IO4 | BE107 | 3.3V |
| P0_IO5 | BF120 | 3.3V |
| P0_IO6 | BE111 | 3.3V |
| P0_IO7 | BF115 | 3.3V |
| P0_IO8 | BH118 | 3.3V |
MIPI CSI-2
The GoldenEagle board has 2 22-pin MIPI CSI-2 connectors (J14 and J16) for MIPI cameras.
CSI0 (J14)
J14 is ZIF FPC connector with 0.5mm pitch. Its pin assignment is listed below: The I2C pins CSI0_SCL/CSI0_SDA are driven from channel 2 of the I2C MUX (U15).
| Signal Name | FPGA Ball | CSI0 J14 | IO Voltage |
|---|---|---|---|
| CSI0_GPIO0 | A17 | 6 | 3.3V |
| CSI0_GPIO1 | BU109 | 5 | 3.3V |
| MUX I2C_SCL | D4 | 3 | 1.8V |
| MUX I2C_SDA | F4 | 2 | 1.8V |
| CSI0_REFCK* | BM71 | 1.1V | |
| CSI0_C_P | BF86 | 14 | 1.1V |
| CSI0_C_N | BE86 | 15 | 1.1V |
| CSI0_D0_P | BE96 | 20 | 1.1V |
| CSI0_D0_N | BE93 | 21 | 1.1V |
| CSI0_D1_P | BF93 | 17 | 1.1V |
| CSI0_D1_N | BF90 | 18 | 1.1V |
| CSI0_D2_P | BE83 | 11 | 1.1V |
| CSI0_D2_N | BF83 | 12 | 1.1V |
| CSI0_D3_P | BE79 | 8 | 1.1V |
| CSI0_D3_N | BE75 | 9 | 1.1V |
* DPHY 25MHz REFCLK (MIPI0_REFCK) from Si5332
CSI1 (J16)
J16 is ZIF FPC connector with 0.5mm pitch. Its pin assignment is listed below: The I2C pins CSI1_SCL/CSI1_SDA are driven from channel 3 of the I2C MUX (U15).
| Signal Name | FPGA Ball | CSI1 J16 | IO Voltage |
|---|---|---|---|
| CSI1_GPIO0 | A20 | 6 | 3.3V |
| CSI1_GPIO1 | BF104 | 5 | 3.3V |
| MUX I2C_SCL | D4 | 3 | 1.8V |
| MUX I2C_SDA | F4 | 2 | 1.8V |
| CSI1_REFCK* | V98 | 1.1V | |
| CSI1_C_P | AG90 | 14 | 1.1V |
| CSI1_C_N | AG93 | 15 | 1.1V |
| CSI1_D0_P | AG100 | 20 | 1.1V |
| CSI1_D0_N | AG104 | 21 | 1.1V |
| CSI1_D1_P | AC100 | 17 | 1.1V |
| CSI1_D1_N | AC96 | 18 | 1.1V |
| CSI1_D2_P | AC90 | 11 | 1.1V |
| CSI1_D2_N | AC86 | 12 | 1.1V |
| CSI1_D3_P | Y98 | 8 | 1.1V |
| CSI1_D3_N | Y95 | 9 | 1.1V |
* DPHY 25MHz REFCLK (MIPI1_REFCK) from Si5332
CRUVI LS C (J20)
The CRUVI LS C (J20) is a dual-row 2mm pitch connector. it is connected to HVIO pins driven at 3.3V.
| Signal Name | FPGA Ball | CRUVI LS J20 |
|---|---|---|
| C0 | BK109 | 3 |
| C1 | BR109 | 5 |
| C2 | BM118 | 7 |
| C3 | BK118 | 9 |
| C4 | BP112 | 4 |
| C5 | BH109 | 8 |
| C6 | BM112 | 1 |
| C7 | BK112 | 2 |
CRUVI HS
There are 2 CRUVI HS connectors (J21 (X), J19 (Y)) on the GoldenEagle board. They are connected to HSIO pins to provide differential signaling. In addition to differential pair signals, CRUVI HS connectors have single-ended signals driven from 3.3V HVIO pin.
HS_X (J21)
| Signal Name | FPGA Ball | CRUVI HS J21 | IO Voltage |
|---|---|---|---|
| CX_REFCLK | BM109 | 11 | 3.3V |
| CX_SMB_ALERT | BR112 | 3 | 3.3V |
| CX_SMB_SCL | A11 | 7 | 3.3V |
| CX_SMB_SDA | B11 | 5 | 3.3V |
| CX_B5_P | P44 | 45 | VIO_CRUVI_T* |
| CX_B5_N | T44 | 47 | VIO_CRUVI_T* |
| CX_B4_P | V58 | 39 | VIO_CRUVI_T* |
| CX_B4_N | T58 | 41 | VIO_CRUVI_T* |
| CX_B3_P | P55 | 33 | VIO_CRUVI_T* |
| CX_B3_N | T55 | 35 | VIO_CRUVI_T* |
| CX_B2_P | K55 | 27 | VIO_CRUVI_T* |
| CX_B2_N | M55 | 29 | VIO_CRUVI_T* |
| CX_A4_P | V47 | 38 | VIO_CRUVI_T* |
| CX_A4_N | T47 | 40 | VIO_CRUVI_T* |
| CX_B0_P | F55 | 15 | VIO_CRUVI_T* |
| CX_B0_N | D55 | 17 | VIO_CRUVI_T* |
| CX_B1_P | M58 | 21 | VIO_CRUVI_T** |
| CX_B1_N | K58 | 23 | VIO_CRUVI_T* |
| CX_A0_P | D44 | 14 | VIO_CRUVI_T* |
| CX_A0_N | F44 | 16 | VIO_CRUVI_T* |
| CX_A1_P | H58 | 20 | VIO_CRUVI_T* |
| CX_A1_N | F58 | 22 | VIO_CRUVI_T* |
| CX_A2_P | F47 | 26 | VIO_CRUVI_T* |
| CX_A2_N | H47 | 28 | VIO_CRUVI_T* |
| CX_A3_P | M47 | 32 | VIO_CRUVI_T* |
| CX_A3_N | K47 | 34 | VIO_CRUVI_T* |
| CX_A5_P | K44 | 44 | VIO_CRUVI_T* |
| CX_A5_N | M44 | 46 | VIO_CRUVI_T* |
| CX_HSIO | B45 | 2 | VIO_CRUVI_T* |
| CX_HSO | A48 | 6 | VIO_CRUVI_T* |
| CX_HSI | A63 | 10 | VIO_CRUVI_T* |
| CX_RESET | A51 | 8 | VIO_CRUVI_T* |
* VIO_CRUVI_T Voltage : 1.2V/1.3V depending on CRUVI_VADJ_T setting of S10B (pin2-7) . S10B OFF = 1.2V, S10B ON = 1.3V
HS_YZ
| Signal Name | FPGA Ball | CRUVI HS J19 | IO Voltage |
|---|---|---|---|
| CY_REFCLK | CL125 | 11 | 3.3V |
| CY_SMB_ALERT | CG134 | 3 | 3.3V |
| CY_SMB_SCL | CD134 | 7 | 3.3V |
| CY_SMB_SDA | CD135 | 5 | 3.3V |
| CY_B5_P | H67 | 45 | VIO_CRUVI_B * |
| CY_B5_N | F67 | 47 | VIO_CRUVI_B * |
| CY_B4_P | F77 | 39 | VIO_CRUVI_B * |
| CY_B4_N | H77 | 41 | VIO_CRUVI_B * |
| CY_B3_P | K77 | 33 | VIO_CRUVI_B * |
| CY_B3_N | M77 | 35 | VIO_CRUVI_B * |
| CY_B2_P | D74 | 27 | VIO_CRUVI_B * |
| CY_B2_N | F74 | 29 | VIO_CRUVI_B * |
| CY_A4_P | M67 | 38 | VIO_CRUVI_B * |
| CY_A4_N | K67 | 40 | VIO_CRUVI_B * |
| CY_B0_P | M74 | 15 | VIO_CRUVI_B * |
| CY_B0_N | K74 | 17 | VIO_CRUVI_B * |
| CY_B1_P | V77 | 21 | VIO_CRUVI_B * |
| CY_B1_N | T77 | 23 | VIO_CRUVI_B * |
| CY_A0_P | T65 | 14 | VIO_CRUVI_B * |
| CY_A0_N | P65 | 16 | VIO_CRUVI_B * |
| CY_A1_P | P74 | 20 | VIO_CRUVI_B * |
| CY_A1_N | T74 | 22 | VIO_CRUVI_B * |
| CY_A2_P | M65 | 26 | VIO_CRUVI_B * |
| CY_A2_N | K65 | 28 | VIO_CRUVI_B * |
| CY_A3_P | V67 | 32 | VIO_CRUVI_B * |
| CY_A3_N | T67 | 34 | VIO_CRUVI_B * |
| CY_A5_P | F65 | 44 | VIO_CRUVI_B * |
| CY_A5_N | D65 | 46 | VIO_CRUVI_B * |
| CY_HSIO | A70 | 2 | VIO_CRUVI_B * |
| CY_HSO | B70 | 6 | VIO_CRUVI_B * |
| CY_HSI | A82 | 10 | VIO_CRUVI_B * |
| CY_RESET | B82 | 8 | VIO_CRUVI_B * |
* VIO_CRUVI_B Voltage : 1.2V/1.3V depending on CRUVI_VADJ_B setting of S10A (pin1-8) . S10A OFF = 1.2V, S10A ON = 1.3V
CRUVI_GTX (J15)
J15 is the Gigabit-speed version of the CRUVI ecosystem that provides a connection surface for peripheral modules using Gigabit Transceivers.
| Signal Name | FPGA Ball | CRUVI GTX J15 | Pin Func. | Description | I/O Std |
|---|---|---|---|---|---|
| GTSR4A_TX0_N | BY10 | A2 | Output | GTSR4A Transceiver TX0_N | CML |
| GTSR4A_TX0_P | BY7 | A3 | Output | GTSR4A Transceiver TX0_N | CML |
| GTSR4A_TX1_N | BT10 | A5 | Output | GTSR4A Transceiver TX0_N | CML |
| GTSR4A_TX1_P | BT7 | A6 | Output | GTSR4A Transceiver TX0_N | CML |
| GTSR4A_TX2_N | BL10 | A8 | Output | GTSR4A Transceiver TX0_N | CML |
| GTSR4A_TX2_P | BL7 | A9 | Output | GTSR4A Transceiver TX0_N | CML |
| GTSR4A_TX3_N | BG10 | A11 | Output | GTSR4A Transceiver TX0_N | CML |
| GTSR4A_TX3_P | BG7 | A12 | Output | GTSR4A Transceiver TX0_N | CML |
| GTSR4A_RX0_N | CB3 | D2 | Input | GTSR4A Transceiver RX0_N | CML |
| GTSR4A_RX0_P | CB1 | D3 | Bidir | GTSR4A Transceiver RX0_P | CML |
| GTSR4A_RX1_N | BV3 | D5 | Bidir | GTSR4A Transceiver RX0_N | CML |
| GTSR4A_RX1_P | BV1 | D6 | Bidir | GTSR4A Transceiver RX0_P | CML |
| GTSR4A_RX2_N | BN3 | D8 | Bidir | GTSR4A Transceiver RX0_N | CML |
| GTSR4A_RX2_P | BN1 | D9 | Bidir | GTSR4A Transceiver RX0_P | CML |
| GTSR4A_RX3_N | BJ3 | D11 | Bidir | GTSR4A Transceiver RX0_N | CML |
| GTSR4A_RX3_P | BJ1 | D12 | Bidir | GTSR4A Transceiver RX0_P | CML |
| GBTCLK0_N | BB21 | D14 | Input | GTSR4A Clock_N | CML |
| GBTCLK0_P | BB16 | D15 | Input | GTSR4A Clock_P | CML |
| LS_IO1 | BK22 | A17 | Bidir | GPIO | 3.3-V LVCMOS |
| LS_IO2 | BU19 | A18 | Bidir | GPIO | 3.3-V LVCMOS |
| LS_IO3 | BM19 | A19 | Bidir | GPIO | 3.3-V LVCMOS |
| LS_IO4 | BR19 | A20 | Bidir | GPIO | 3.3-V LVCMOS |
| LS_IO5 | CK2 | D17 | - | GPIO | 3.3-V LVCMOS |
| LS_IO6 | CJ2 | D18 | - | GPIO | 3.3-V LVCMOS |
| LS_IO7 | CK4 | D19 | - | GPIO | 3.3-V LVCMOS |
| LS_IO8 | CH4 | D20 | - | GPIO | 3.3-V LVCMOS |
| LS_SCL | BF25 | B19 | - | I2C Clock Signal | 3.3-V LVCMOS |
| LS_SDA | BF16 | B20 | - | I2C Data SIgnal | 3.3-V LVCMOS |
| HS_D5_N | Y47 | B16 | Bidir | Clock-Capable Differential Signal | Adjustable** |
| HS_D5_P | Y44 | B17 | Bidir | Clock-Capable Differential Signal | Adjustable** |
| HS_D11_N | AG53 | C16 | Bidir | Differential Signal | Adjustable** |
| HS_D11_P | AG57 | C17 | Bidir | Differential Signal | Adjustable** |
** “1.2V True Differential Signaling” or “1.3V True Differential Signaling”. Depending on VIO_CRUVI_T
M.2 nVME Socket (U22)
The development kit supports a single NVME interface via a Key M socket.
| Signal Name | FPGA Ball | U22 Socket | Pin Func. | Description | I/O Std |
|---|---|---|---|---|---|
| GTSL1C_TX0_P | AU129 | 49 | Output | Transmitter data | High Speed Differential I/O |
| GTSL1C_TX0_N | AU126 | 47 | Output | Transmitter data | High Speed Differential I/O |
| GTSL1C_RX0_P | AT135 | 43 | Input | Receiver data | High Speed Differential I/O |
| GTSL1C_RX0_N | AT133 | 41 | Input | Receiver data | High Speed Differential I/O |
| SSD_RCLK_P | - | - | - | 100MHz from Si5332A (U10) | LVDS 1.8V |
| SSD_RCLK_N | - | - | - | 100MHz from Si5332A (U10) | LVDS 1.8V |
| SSD1_PERSTn | CF128 | 50 | Input | PCIe Reset | 3.3-V LVCMOS |
| SSD1_CLKRQ | A14 | 52 | Input | Clock Request | 3.3-V LVCMOS |
| SSD1_WAKE | B14 | 54 | Output | Wake from low-power state | 3.3-V LVCMOS |
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