AXE5 Falcon connector pinout - ArrowElectronics/Agilex-5 GitHub Wiki

AXE5-Falcon Connector Pin Assignments

HDMI Output

The HDMI connector (J7) is driven by a Texas Instruments TFP410PAP HDMI Transmitter device. The TFP410PAP is driven from the SoC FPGA with a parallel 24-bit bus and control signals described in the table below. All signals are driven from HVIO banks powered at 1.8V.

HDMI Signal	FPGA Ball	HDMI Signal	FPGA Ball
HDMI_SCL	CR8	HDMI_SDA	DD3
CT_HPD	DN2	HDMI_PD	DM2
HDMI_HTPLG	DF3	HDMI_CLK	CE19
HDMI_HS	DH1	HDMI_VS	DC1
HDMI_DE	DE1
HDMI_D0	DH2	HDMI_D1	DC2
HDMI_D2	CV4	HDMI_D3	CV6
HDMI_D4	CV11	HDMI_D5	CV14
HDMI_D6	CV16	HDMI_D7	CV19
HDMI_D8	CR11	HDMI_D9	CR14
HDMI_D10	CR19	HDMI_D11	CH16
HDMI_D12	CH19	HDMI_D13	CH14
HDMI_D14	CG23	HDMI_D15	CE14
HDMI_D16	CG26	HDMI_D17	CD23
HDMI_D18	CH4	HDMI_D19	CA23
HDMI_D20	BV11	HDMI_D21	BV19
HDMI_D22	BV16	HDMI_D23	BV14

RJ-45 Connectors (J3)

There is 1 RJ-45 Ethernet connector on the AXE5-Falcon board which is driven by KSZ9031 Gigabit Ethernet PHY device. The PHY device is driven by the RGMII signals described below.

The KSX9031 is driven from the HPS EMAC2 connected to the HPS MUX and driven at 1.8V logic levels.

Signal Name	FPGA Ball	Signal Name	FPGA Ball
ETH_RST	P75
ETH_MDC	AK67	ETH_MDIO	U74
ETH_TXCK	L75	ETH_RXCK	N71
ETH_TXCTL	N72	ETH_RXCTL	AD72
ETH_TXD0	F75	ETH_RXD0	K71
ETH_TXD1	AD71	ETH_RXD1	AK71
ETH_TXD2	F74	ETH_RXD2	C74
ETH_TXD3	AA71	ETH_RXD3	D71

SD Card Connector (J24)

The SD Card interface comes from the HPS MUX pins which are powered by a 1.8V rail. The SD_DETECT is implemented using an HPS GPIO. All pins, except SD_DETECT, go through a level translator between the SoC FPGA 1.8V rail to the connector's 3.3V rail.

Signal Name	FPGA Ball
SD_CLK	AC74
SD_CMD	AK69
SD_DETECT	P74
SD_DAT0	AF75
SD_DAT1	AC75
SD_DAT2	AN64
SD_DAT3	Y74

USB Type-A

The Quad-USB Type A connectors are driven from a Microchip 4-port USB HUB (USB2514B). This HUB interfaces to the SoC FPGA via USB ULP PHY (USB3320C) interface.

The ULPI signals are connected to the HPS MUX.

USB interface signals:

Signal Name	FPGA Ball
USB_STP	BC67
USB_NXT	BA75
USB_DIR	AY67
USB_CLK	BC64
USB_RST	Y75
USB_DATA0	AN72
USB_DATA1	AY69
USB_DATA2	BC71
USB_DATA3	AU74
USB_DATA4	AY71
USB_DATA5	AU75
USB_DATA6	BC72
USB_DATA7	BP74

USB-C (UART) Connector (J25)

J25 is connected to 2 UARTs in the FPGA, one is UART0 of the HPS MUX and the other is an optional debug UART, via an FTDI USB to UART bridge device (FT4232H).

Signal Name	FPGA Ball
UART0_TX	AJ84
UART0_RX	AJ75
DBG_TXD	AJ2
DBG_RXD	AJ1

MIPI CSI-2

The Falcon board has 2 22-pin MIPI CSI-2 connectors (J8 and J9) for a camera.

CSI0 (J8)

J8 is ZIF FPC connector with 0.5mm pitch. Its pin assignment is listed below: The I2C pins CSI0_SCL/CSI0_SDA are driven from channel 2 of the I2C MUX (U45).

Signal Name	FPGA Ball	IO Voltage
CSI0_GPIO0	AE11	3.3V
CSI0_GPIO1	R6	3.3V
MUX I2C_SCL	AC2	1.8V
MUX I2C_SDA	AC1	1.8V
CSI0_C_P	DP15	VCCIO_2A_T*
CSI0_C_N	DN15	VCCIO_2A_T*
CSI0_D0_P	DP20	VCCIO_2A_T*
CSI0_D0_N	DN17	VCCIO_2A_T*
CSI0_D1_P	DP22	VCCIO_2A_T*
CSI0_D1_N	DN20	VCCIO_2A_T*
CSI0_D2_P	DP10	VCCIO_2A_T*
CSI0_D2_N	DP13	VCCIO_2A_T*
CSI0_D3_P	DP7	VCCIO_2A_T*
CSI0_D3_N	DN10	VCCIO_2A_T*

1.2V/1.3V depending on J17 setting. J17-1 to J17-2 = 1.2V, J17-2 to J17-3 = 1.3V AND SEL_1V3 I/O pin (1.8V FPGA pin BE8) = '1'

CSI1 (J9)

J9 is ZIF FPC connector with 0.5mm pitch. Its pin assignment is listed below: The I2C pins CSI1_SCL/CSI1_SDA are driven from channel 1 of the I2C MUX (U45).

Signal Name	FPGA Ball	IO Voltage
CSI1_GPIO0	AV6	3.3V
CSI1_GPIO1	AV4	3.3V
MUX I2C_SCL	AC2	1.8V
MUX I2C_SDA	AC1	1.8V
CSI1_C_P	DP15	VCCIO_2A_T*
CSI1_C_N	DN15	VCCIO_2A_T*
CSI1_D0_P	DJ21	VCCIO_2A_T*
CSI1_D0_N	DF21	VCCIO_2A_T*
CSI1_D1_P	DD21	VCCIO_2A_T*
CSI1_D1_N	DD18	VCCIO_2A_T*
CSI1_D2_P	DJ12	VCCIO_2A_T*
CSI1_D2_N	DF12	VCCIO_2A_T*
CSI1_D3_P	DD12	VCCIO_2A_T*
CSI1_D3_N	DD9	VCCIO_2A_T*

1.2V/1.3V depending on J17 setting. J17-1 to J17-2 = 1.2V, J17-2 to J17-3 = 1.3V AND SEL_1V3 I/O pin (1.8V FPGA pin BE8) = '1'

PMOD

The dual-row PMOD connector (J16) is connected to HVIO pins driven at 3.3V.

Signal Name	FPGA Ball	PMOD Pin
P0_IO1	AH11	1
P0_IO2	AE8	2
P0_IO3	AE6	3
P0_IO4	V4	4
P0_IO5	AH14	7
P0_IO6	V6	8
P0_IO7	V11	9
P0_IO8	AG23	10

Pi Hat

The Falcon board provides a through hole footprint for a Pi Hat header (J4). It is connected to FPGA HVIO pins driven at 3.3V.

Signal Name	FPGA Ball	PiHat Pin	Signal Name	FPGA Ball	PiHat Pin
ID_SCL	L1	28	ID_SDA	C6	27
GPIO2	C14	2	GPIO3	A13	5
GPIO4	C11	7	GPIO5	P2	29
GPIO6	P1	31	GPIO7	B5	26
GPIO8	A10	24	GPIO9	B15	21
GPIO10	AH19	19	GPIO11	C8	23
GPIO12	F2	32	GPIO13	U2	33
GPIO14	A15	8	GPIO15	B10	10
GPIO16	V16	36	GPIO17	H16	11
GPIO18	B3	12	GPIO19	Y1	35
GPIO20	Y2	38	GPIO21	C2	40
GPIO22	H14	15	GPIO23	H6	16
GPIO24	H4	18	GPIO25	R14	22
GPIO26	AH16	37	GPIO27	H11	13

CRUVI LS C

The CRUVI LS C (J20) is a dual-row 2mm pitch connector. it is connected to HVIO pins driven at 3.3V.

Signal Name	FPGA Ball	CRUVI LS Pin
C0	BE11	3
C1	BR11	5
C2	BH16	7
C3	BH19	9
C4	BR19	4
C5	BH11	8
C6	BE14	1
C7	BR14	2

CRUVI HS

There are 3 CRUVI HS connectors (J1 (Z), J19 (Y), J21 (X)) on the Falcon board. J1 and J21 (X and Z) are connected to HSIO pins In addition to differential pair signals, CRUVI HS connectors have single-ended signals driven from 3.3V HVIO pin.

HS_X

Signal Name	FPGA Ball	CRUVI HS J21	IO Voltage
CX_REFCLK	CH6	11	3.3V
CX_SMB_ALERT	CE8	3	3.3V
CX_SMB_SCL	CE6	7	3.3V
CX_SMB_SDA	DJ3	5	3.3V
CX_B5_P	DD27	45	VCCIO_2A_T*
CX_B5_N	DD24	47	VCCIO_2A_T*
CX_B4_P	DD35	39	VCCIO_2A_T*
CX_B4_N	DD32	41	VCCIO_2A_T*
CX_B3_P	DJ35	33	VCCIO_2A_T*
CX_B3_N	DF35	35	VCCIO_2A_T*
CX_B2_P	DK32	27	VCCIO_2A_T*
CX_B2_N	DJ32	29	VCCIO_2A_T*
CX_A4_P	DJ27	38	VCCIO_2A_T*
CX_A4_N	DF27	40	VCCIO_2A_T*
CX_B0_P	DK39	15	VCCIO_2A_B*
CX_B0_N	DJ39	17	VCCIO_2A_B*
CX_B1_P	DP61	21	VCCIO_2A_B**
CX_B1_N	DN61	23	VCCIO_2A_B*
CX_A0_P	DP60	14	VCCIO_2A_B*
CX_A0_N	DN58	16	VCCIO_2A_B*
CX_A1_P	DP70	20	VCCIO_2A_B*
CX_A1_N	DN68	22	VCCIO_2A_B*
CX_A2_P	DN73	26	VCCIO_2A_B*
CX_A2_N	DN74	28	VCCIO_2A_B*
CX_A3_P	DP66	32	VCCIO_2A_B*
CX_A3_N	DN63	34	VCCIO_2A_B*
CX_A5_P	DP68	44	VCCIO_2A_B*
CX_A5_N	DN66	46	VCCIO_2A_B*
CX_HSIO	DJ42	2	VCCIO_2A_B*
CX_HSO	DF42	6	VCCIO_2A_B*
CX_HSI	DP47	10	VCCIO_2A_B*
CX_RESET	DN43	8	VCCIO_2A_B*

VCCIO_2A_T Voltage : 1.2V/1.3V depending on J17 setting. J17-1 to J17-2 = 1.2V, J17-2 to J17-3 = 1.3V AND SEL_1V3 I/O pin (1.8V FPGA pin BE8) = '1'
VCCIO_2A_B Voltage : 1.3V when SEL_1V3 I/O pin (1.8V FPGA pin BE8) = '1', else 1.2V

HS_Z

Signal Name	FPGA Ball	CRUVI HS J1	IO Voltage
CZ_REFCLK	BF23	11	3.3V
CZ_SMB_ALERT	AV14	3	3.3V
CZ_SMB_SCL	AV11	7	3.3V
CZ_SMB_SDA	AV16	5	3.3V
CZ_B5_P	DP25	45	VCCIO_2A_T*
CZ_B5_N	DN25	47	VCCIO_2A_T*
CZ_B4_P	DP38	39	VCCIO_2A_T*
CZ_B4_N	DN38	41	VCCIO_2A_T*
CZ_B3_P	DP36	33	VCCIO_2A_T*
CZ_B3_N	DN33	35	VCCIO_2A_T*
CZ_B2_P	DP33	27	VCCIO_2A_T*
CZ_B2_N	DN30	29	VCCIO_2A_T*
CZ_A4_P	DP30	38	VCCIO_2A_T*
CZ_A4_N	DN28	40	VCCIO_2A_T*
CZ_B0_P	DP23	15	VCCIO_2A_B*
CZ_B0_N	DN22	17	VCCIO_2A_B*
CZ_B1_P	DD59	21	VCCIO_2A_B*
CZ_B1_N	DD56	23	VCCIO_2A_B*
CZ_A0_P	DK56	14	VCCIO_2A_B*
CZ_A0_N	DJ56	16	VCCIO_2A_B*
CZ_A1_P	DJ65	20	VCCIO_2A_B*
CZ_A1_N	DF65	22	VCCIO_2A_B*
CZ_A2_P	DD65	26	VCCIO_2A_B*
CZ_A2_N	DD62	28	VCCIO_2A_B*
CZ_A3_P	DJ59	32	VCCIO_2A_B*
CZ_A3_N	DF59	34	VCCIO_2A_B*
CZ_A5_P	DK62	44	VCCIO_2A_B*
CZ_A5_N	DJ62	46	VCCIO_2A_B*
CZ_HSIO	DJ48	2	VCCIO_2A_B*
CZ_HSO	DK48	6	VCCIO_2A_B*
CZ_HSI	DJ51	10	VCCIO_2A_B*
CZ_RESET	DD48	8	VCCIO_2A_B*

VCCIO_2A_T Voltage : 1.2V/1.3V depending on J17 setting. J17-1 to J17-2 = 1.2V, J17-2 to J17-3 = 1.3V AND SEL_1V3 I/O pin (1.8V FPGA pin BE8) = '1'
VCCIO_2A_B Voltage : 1.3V when SEL_1V3 I/O pin (1.8V FPGA pin BE8) = '1', else 1.2V

HS_Y

J19 uses a CRUVI HS connector, but all of its signals are single-ended driven from 1.8V HVIO pins. It is wired to support 2 additional Ethernet ports. However, other CRUVI-HS boards which use a 1.8V interface can be used. The Trenz CR00200-01 and CR00202-01

Signal Name	FPGA Ball	CY Pin	Signal Name	FPGA Ball	CY Pin
RGMII_RESET	BR6	8	RGMII_IRQ	BW2	10
RGMII_MDC	BW1	6	RGMII_MDIO	CB2	2
RGMII0_TX_CK	CJ1	21	RGMII1_TX_CK	AU2	45
RGMII0_RX_CK	CF2	27	RGMII1_RX_CK	AP1	44
RGMII0_TX_CTRL	CJ2	23	RGMII1_TX_CTRL	AU1	47
RGMII0_RX_CTRL	CF1	29	RGMII1_RX_CTRL	AP2	46
RGMII0_TXD0	DA1	39	RGMII1_TXD0	BL2	20
RGMII0_TXD1	DA2	41	RGMII1_TXD1	BL1	22
RGMII0_TXD2	CU2	32	RGMII1_TXD2	BH4	26
RGMII0_TXD3	BV6	34	RGMII1_TXD3	BG2	28
RGMII0_RXD0	CP1	38	RGMII1_RXD0	BD2	14
RGMII0_RXD1	CP2	40	RGMII1_RXD1	BD1	16
RGMII0_RXD2	CM1	33	RGMII1_RXD2	BH6	15
RGMII0_RXD3	BV4	35	RGMII1_RXD3	BA1	17

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