AXE5 Eagle connector pinout - ArrowElectronics/Agilex-5 GitHub Wiki

AXE5-Eagle Connector Pin Assignments

FMC+ Connector

The FMC+ is a High Serial Pin Connector (HSPC) with 560 pins arranged in a 14x40 array. Only the colored signal boxes listed in the diagram below are connected to the Agilex 5.

A mezzanine board with an FMC HSPC (red region) can be used if the user doesn't need the signals in column L.

The connector image and a tabular pin assignment are shown below:

FMC+ (J3) Pinout

Note: The LA00-LA33 pins are connected to an HSIO bank on the Agilex-5. This bank can only be powered by a 1.2V or 1.3V power source. If using the LA00-LA33 pins as differential pairs, the VCCIO must be set to 1.3V via a DIP switch S10. For 1.3V, The FMC_ADJ_SEL DIP switch should be in the ON position as shown below.

FMC+ Pin FPGA Ball Signal Name VCCIO FMC+ Pin FPGA Ball Signal Name VCCIO
A1 GND B1 CLK_DIR
A2 GTSR4B_RX_CH1P (BD1) DP1_M2C_P 1.0V B2 GND
A3 GTSR4B_RX_CH1N (BD3) DP1_M2C_N 1.0V B3 GND
A4 GND B4
A5 GND B5
A6 GTSR4B_RX_CH2P (BB1) DP2_M2C_P 1.0V B6 GND
A7 GTSR4B_RX_CH2N (BB3) DP2_M2C_N 1.0V B7 GND
A8 GND B8
A9 GND B9
A10 GTSR4B_RX_CH3P (AY1) DP3_M2C_P 1.0V B10 GND
A11 GTSR4B_RX_CH3N (AY3) DP3_M2C_N 1.0V B11 GND
A12 GND B12 GTSR4C_RX_CH3P (AM1) DP7_M2C_P 1.0V
A13 GND B13 GTSR4C_RX_CH3N (AM3) DP7_M2C_N 1.0V
A14 GTSR4C_RX_CH0P (AV1) DP4_M2C_P 1.0V B14 GND
A15 GTSR4C_RX_CH0N (AV3) DP4_M2C_N 1.0V B15 GND
A16 GND B16 GTSR4C_RX_CH2P (AP1) DP6_M2C_P 1.0V
A17 GND B17 GTSR4C_RX_CH2N (AP3) DP6_M2C_N 1.0V
A18 GTSR4C_RX_CH1P (AT1) DP5_M2C_P 1.0V B18 GND
A19 GTSR4C_RX_CH1N (AT3) DP5_M2C_N 1.0V B19 GND
A20 GND B20 REFCLK_GTSR4C_CH1P (AP16) GBTCLK1_M2C_P 1.0V
A21 GND B21 REFCLK_GTSR4C_CH1N (AP21) GBTCLK1_M2C_N 1.0V
A22 GTSR4B_TX_CH1P (BC7) DP1_C2M_P 1.0V B22 GND
A23 GTSR4B_TX_CH1N (BC10) DP1_C2M_N 1.0V B23 GND
A24 GND B24
A25 GND B25
A26 GTSR4B_TX_CH2P (BA7) DP2_C2M_P 1.0V GND
A27 GTSR4B_TX_CH2N (BA10) DP2_C2M_N 1.0V GND
A28 GND B28
A29 GND B29
A30 GTSR4B_TX_CH3P (AW7) DP3_C2M_P 1.0V B30 GND
A31 GTSR4B_TX_CH3N (AW10) DP3_C2M_N 1.0V B31 GND
A32 GND B32 GTSR4C_TX_CH3P (AL7) DP7_C2M_P 1.0V
A33 GND B33 GTSR4C_TX_CH3N (AL10) DP7_C2M_N 1.0V
A34 GTSR4C_TX_CH0P (AU7) DP4_C2M_P 1.0V B34 GND
A35 GTSR4C_TX_CH0N (AU10) DP4_C2M_N 1.0V B35 GND
A36 GND B36 GTSR4C_TX_CH2P (AN7) DP6_C2M_P 1.0V
A37 GND B37 GTSR4C_TX_CH2N (AN10) DP6_C2M_N 1.0V
A38 GTSR4C_TX_CH1P (AR7) DP5_C2M_P 1.0V B38 GND
A39 GTSR4C_TX_CH1N (AR10) DP5_C2M_N 1.0V B39 GND
A40 GND B40 3P3V 3.3V
FMC+ Pin FPGA Ball Signal Name VCCIO FMC+ Pin FPGA Ball Signal Name VCCIO
C1 GND D1 PG_GROUP3 (3.3V rail) PG_C2M
C2 GTSR4B_TX_CH0P (BE7) DP0_C2M_P 1.0V D2 GND
C3 GTSR4B_TX_CH0N (BE10) DP0_C2M_N 1.0V D3 GND
C4 GND D4 REFCLK_GTSR4B_CH1P (AV16) GBTCLK0_M2C_P 1.0V
C5 GND D5 REFCLK_GTSR4B_CH1N (AV21) GBTCLK0_M2C_N 1.0V
C6 GTSR4B_RX_CH0P (BF1) DP0_M2C_P 1.0V D6 GND
C7 GTSR4B_RX_CH0N (BF3) DP0_M2C_N 1.0V D7 GND
C8 GND D8 CF22 LA01_P 1.2/1.3V
C9 GND D9 CH22 LA01_N 1.2/1.3V
C10 CK8 LA06_P 1.2/1.3V D10 GND
C11 CL6 LA06_N 1.2/1.3V D11 CH31 LA05_P 1.2/1.3V
C12 GND D12 CF31 LA05_N 1.2/1.3V
C13 GND D13 GND
C14 CL20 LA10_P 1.2/1.3V D14 CK17 LA09_P 1.2/1.3V
C15 CK20 LA10_N 1.2/1.3V D15 CL17 LA09_N 1.2/1.3V
C16 GND D16 GND
C17 GND D17 BF57 LA13_P 1.2/1.3V
C18 BE46 LA14_P 1.2/1.3V D18 BF53 LA13_N 1.2/1.3V
C19 BF46 LA14_N 1.2/1.3V D19 GND
C20 GND D20 BR41 LA17_P 1.2/1.3V
C21 GND D21 BU41 LA17_N 1.2/1.3V
C22 BK49 LA18_P 1.2/1.3V D22 GND
C23 BM49 LA18_N 1.2/1.3V D23 BW49 LA23_P 1.2/1.3V
C24 GND D24 CA49 LA23_N 1.2/1.3V
C25 GND D25 GND
C26 CC52 LA27_P 1.2/1.3V D26 BM52 LA26_P 1.2/1.3V
C27 CA52 LA27_N 1.2/1.3V D27 BP52 LA26_N 1.2/1.3V
C28 GND D28 GND
C29 GND D29 FMC_TCK
C30 FMC_SCL 3.3V D30 FMC_TDI
C31 FMC_SDA 3.3V D31 FMC_TDO
C32 GND D32 3.3V_AUX 3.3V
C33 GND D33 FMC_TMS
C34 GND (GA0) D34 GND FMC_TRST_L
C35 12P0V 12.0V D35 GND
C36 GND D36 3P3V 3.3V
C37 12P0V 12.0V D37 GND
C38 GND D38 3P3V 3.3V
C39 3P3V 3.3V D39 GND
C40 GND D40 3P3V 3.3V
FMC+ Pin FPGA Ball Signal Name VCCIO FMC+ Pin FPGA Ball Signal Name VCCIO
E1 GND F1 PG_M2C
E2 F2 GND
E3 F3 GND
E4 GND F4
E5 GND F5
E6 F6 GND
E7 F7
E8 GND F8
E9 F9 GND
E10 F10
E11 GND F11
E12 F12 GND
E13 F13
E14 GND F14
E15 F15 GND
E16 F16
E17 GND F17
E18 F18 GND
E19 F19
E20 GND F20
E21 F21 GND
E22 F22
E23 GND F23
E24 F24 GND
E25 F25
E26 GND F26
E27 F27 GND
E28 F28
E29 GND F29
E30 F30 GND
E31 F31
E32 GND F32
E33 F33 GND
E34 F34
E35 GND F35
E36 F36 GND
E37 F37
E38 GND F38
E39 VADJ F39 GND
E40 GND F40 VADJ
FMC+ Pin FPGA Ball Signal Name VCCIO FMC+ Pin FPGA Ball Signal Name VCCIO
G1 GND H1 VREF_A_M2C
G2 REFCLK_GTSR4C_RX_P (AT16) FMC_CK1_M2C_P 1.0V H2 PRSNT_M2C_L
G3 REFCLK_GTSR4C_RX_N (AT21) FMC_CK1_M2C_N 1.0V H3 GND
G4 GND H4 REFCLK_GTSR4B_RX_P (AY16) FMC_CK0_M2C_P 1.0V
G5 GND H5 REFCLK_GTSR4B_RX_N (AY21) FMC_CK0_M2C_N 1.0V
G6 CF19 LA00_P 1.2/1.3V H6 GND
G7 CC19 LA00_N 1.2/1.3V H7 CC22 LA02_P 1.2/1.3V
G8 GND H8 CA22 LA02_N 1.2/1.3V
G9 CF28 LA03_P 1.2/1.3V H9 GND
G10 CC28 LA03_N 1.2/1.3V H10 CA31 LA04_P 1.2/1.3V
G11 GND H11 CC31 LA04_N 1.2/1.3V
G12 CL14 LA08_P 1.2/1.3V H12 GND
G13 CL11 LA08_N 1.2/1.3V H13 CK11 LA07_P 1.2/1.3V
G14 GND H14 CL8 LA07_N 1.2/1.3V
G15 BH38 LA12_P 1.2/1.3V H15 GND
G16 BH41 LA12_N 1.2/1.3V H16 CL23 LA11_P 1.2/1.3V
G17 GND H17 CK26 LA11_N 1.2/1.3V
G18 BF50 LA16_P 1.2/1.3V H18 GND
G19 BE50 LA16_N 1.2/1.3V H19 BE64 LA15_P 1.2/1.3V
G20 GND H20 BF64 LA15_N 1.2/1.3V
G21 CA38 LA20_P 1.2/1.3V H21 GND
G22 BW38 LA20_N 1.2/1.3V H22 CK73 LA19_P 1.2/1.3V
G23 GND H23 CL73 LA19_N 1.2/1.3V
G24 CF49 LA22_P 1.2/1.3V H24 GND
G25 CH49 LA22_N 1.2/1.3V H25 BR38 LA21_P 1.2/1.3V
G26 GND H26 BU38 LA21_N 1.2/1.3V
G27 CL51 LA25_P 1.2/1.3V H27 GND
G28 CK54 LA25_N 1.2/1.3V H28 CF52 LA24_P 1.2/1.3V
G29 GND H29 CH52 LA24_N 1.2/1.3V
G30 CK33 LA29_P 1.2/1.3V H30 GND
G31 CL30 LA29_N 1.2/1.3V H31 BP41 LA28_P 1.2/1.3V
G32 GND H32 BM41 LA28_N 1.2/1.3V
G33 CK39 LA31_P 1.2/1.3V H33 GND
G34 CL39 LA31_N 1.2/1.3V H34 CK35 LA30_P 1.2/1.3V
G35 GND H35 CL35 LA30_N 1.2/1.3V
G36 CL42 LA33_P 1.2/1.3V H36 GND
G37 CK45 LA33_N 1.2/1.3V H37 CK48 LA32_P 1.2/1.3V
G38 GND H38 CL45 LA32_N 1.2/1.3V
G39 VADJ H39 GND
G40 GND H40 VADJ
FMC+ Pin FPGA Ball Signal Name FMC+ Pin FPGA Ball Signal Name
J1 GND K1 VREF_B_M2C
J2 K2 GND
J3 K3 GND
J4 GND K4
J5 GND K5
J6 K6 GND
J7 K7
J8 GND K8
J9 K9 GND
J10 K10
J11 GND K11
J12 K12 GND
J13 K13
J14 GND K14
J15 K15 GND
J16 K16
J17 GND K17
J18 K18 GND
J19 K19
J20 GND K20
J21 K21 GND
J22 K22
J23 GND K23
J24 K24 GND
J25 K25
J26 GND K26
J27 K27 GND
J28 K28
J29 GND K29
J30 K30 GND
J31 K31
J32 GND K32
J33 K33 GND
J34 K34
J35 GND K35
J36 K36 GND
J37 K37
J38 GND K38
J39 VIO_B_M2C K39 GND
J40 GND K40 VIO_B_M2C
FMC+ Pin FPGA Ball Signal Name VCCIO FMC+ Pin FPGA Ball Signal Name VCCIO
L1 RES1 M1 GND
L2 GND M2
L3 GND M3
L4 M4 GND
L5 M5 GND
L6 GND M6
L7 GND M7
L8 M8 GND
L9 M9 GND
L10 GND M10
L11 GND M11
L12 M12 GND
L13 M13 GND
L14 GND M14
L15 GND M15
L16 DIFF_IO_2B_B9P (CH41) SYNC_C2M_P 1.0V M16 GND
L17 DIFF_IO_2B_B9N (CF41) SYNC_C2M_N 1.0V M17 GND
L18 GND M18
L19 GND M19
L20 DIFF_IO_2B_T16P (BE61) REFCLK_C2M_P 1.0V M20 GND
L21 DIFF_IO_2B_T16N (BE57) REFCLK_C2M_N 1.0V M21 GND
L22 GND M22
L23 GND M23
L24 CLK_B_2B_0P (CH38) REFCLK_M2C_P 1.0V M24 GND
L25 CLK_B_2B_0N (CF38) REFCLK_M2C_N 1.0V M25 GND
L26 GND M26
L27 GND M27
L28 DIFF_IO_2B_T23P (BH49) SYNC_M2C_P 1.0V M28 GND
L29 DIFF_IO_2B_T23N (BH52) SYNC_M2C_N 1.0V M29 GND
L30 GND M30
L31 GND M31
L32 RES2 M32 GND
L33 RES3 M33 GND
L34 GND M34
L35 GND M35
L36 12P0V 12.0V M36 GND
L37 12P0V 12.0V M37 GND
L38 GND M38
L39 GND M39
L40 12P0V 12.0V M40 GND
FMC+ Pin FPGA Ball Signal Name FMC+ Pin FPGA Ball Signal Name
Z1 3.3V pullup PRSNT_M2C_L Y1 GND
Z2 GND Y2
Z3 GND Y3
Z4 Y4 GND
Z5 Y5 GND
Z6 GND Y6
Z7 GND Y7
Z8 Y8 GND
Z9 Y9 GND
Z10 GND Y10
Z11 GND Y11
Z12 Y12 GND
Z13 Y13 GND
Z14 GND Y14
Z15 GND Y15
Z16 Y16 GND
Z17 Y17 GND
Z18 GND Y18
Z19 GND Y19
Z20 Y20 GND
Z21 Y21 GND
Z22 GND Y22
Z23 GND Y23
Z24 Y24 GND
Z25 Y25 GND
Z26 GND Y26
Z27 GND Y27
Z28 Y28 GND
Z29 Y29 GND
Z30 GND Y30
Z31 GND Y31
Z32 Y32 GND
Z33 Y33 GND
Z34 GND Y34
Z35 GND Y35
Z36 Y36 GND
Z37 Y37 GND
Z38 GND Y38
Z39 GND Y39
Z40 3P3V Y40 GND

SFP+ Connector

There are 2x SFP+ connectors on the AXE5-Eagle board and they are both connected to the same IO bank on the SoC FPGA. However, an HSIO bank can support only 1x 10Gb Ethernet Hard IP per bank. This means that if the user needs to use both 10Gb Ethernet ports, one will have to use a Soft IP.

The SFP+ control signals go through a 1.2V to 3.3V level translator between the SoC FPGA and the connector. Similarly, the MUX_I2C signals go through a 1.8V to 3.3V level translation through the I2C MUX.

SFPA Signal FPGA Ball VCCIO
SFPA_TX_DIS Y77 1.2V
SFPA_TX_FAULT Y74 1.2V
SFPA_RS1 Y58 1.2V
SFPA_RS0 AC64 1.2V
SFPA_LOS AG64 1.2V
SFPA_M-DEF0 A80 1.2V
SFPA_SDA* MUX_I2C_SDA (F4) 1.8V
SFPA_SCL* MUX_I2C_SCL (D4) 1.8V
SFPA_TD_P GTSL1C_TX_CH0P (AU129)
SFPA_TD_N GTSL1C_TX_CH0N (AU126)
SFPA_RD_P GTSL1C_RX_CH0P (AT135)
SFPA_RD_N GTSL1C_RX_CH0N (AT133)
SFPB Signal FPGA Ball VCCIO
SFPB_TX_DIS AC50 1.2V
SFPB_TX_FAULT Y55 1.2V
SFPB_RS1 AC53 1.2V
SFPB_RS0 AG57 1.2V
SFPB_LOS AC61 1.2V
SFPB_M-DEF0 AG83 1.2V
SFPB_SDA* MUX_I2C_SDA (F4) 1.8V
SFPB_SCL* MUX_I2C_SCL (D4) 1.8V
SFPB_TD_P GTSL1C_TX_CH3P (AL129)
SFPB_TD_N GTSL1C_TX_CH3N (AL126)
SFPB_RD_P GTSL1C_RX_CH3P (AK135)
SFPB_RD_N GTSL1C_RX_CH3N (AK133)

*Note: The user must set up the TCA9544A I2C MUX to select the appropriate SFP+ port to communicate with.

HDMI Output

The HDMI connector (J11) is driven by an Analog Device ADV7511W HDMI Transmitter device. The ADV7511W is driven from the SoC FPGA with a parallel 24-bit bus and control signals described in the table below. All signals are driven from HVIO banks powered at 1.8V.

The HDMI I2C signals are driven by the I2C MUX (see TCA9544A above).

HDMI Signal FPGA Ball
HDMI_I2C_SCL MUX_I2C_SCL (D4)
HDMI_I2C_SDA MUX_I2C_SDA (F4)
CEC_CLK BF25
CT_HPD BW19
HDMI_CLK BK31
HDMI_HS CF12
HDMI_VS BH19
HDMI_DE BK19
HDMI_INT BF16
HDMI_D0 BF32
HDMI_D1 CH12
HDMI_D2 BM22
HDMI_D3 BF21
HDMI_D4 BE21
HDMI_D5 BP22
HDMI_D6 BR22
HDMI_D7 BE25
HDMI_D8 BU22
HDMI_D9 BW28
HDMI_D10 BU28
HDMI_D11 BM31
HDMI_D12 BR28
HDMI_D13 BM28
HDMI_D14 BK28
HDMI_D15 BH28
HDMI_D16 BF36
HDMI_D17 BE43
HDMI_D18 BU31
HDMI_D19 BP31
HDMI_D20 BR31
HDMI_D21 BF29
HDMI_D22 BF40
HDMI_D23 BE29

RJ-45 Connectors (J4 and J28)

There are 2 RJ-45 Ethernet connectors on the AXE5-Eagle board which are driven by ADIN1300 Ethernet PHY devices. Each of the PHY devices is driven by the RGMII signals described below.

The RJ45 (J4) is driven from the HPS EMAC2 connected to the HPS MUX and driven at 1.8V logic levels.

Signal Name FPGA Ball
ETH_RST T124
ETH_MDC Y132
ETH_MDIO T127
ETH_TXCK M127
ETH_TXCTL K127
ETH_RXCK M124
ETH_RXCTL AB127
ETH_TXD0 K124
ETH_TXD1 Y127
ETH_TXD2 F127
ETH_TXD3 Y124
ETH_RXD0 H127
ETH_RXD1 AB124
ETH_RXD2 F124
ETH_RXD3 D124

The RJ45 (J28) is driven from the FPGA Fabric with HVIO powered by a 1.8V voltage source. This can be driven by HPS EMAC0 (through the FPGA fabric) or by an Ethernet Triple Speed Ethernet (TSE) IP in the FPGA.

The interface to the HPS EMAC0 requires that the ETH1_RXCK and ETH1_RXD1 pins are swapped. This is implemented in the AXE5-Eagle-ES release. HPS EMAC0 functionality will not be available with the AXE5-Eagle-ES0 release.

Signal Name FPGA Ball
ETH1_RST F27
ETH1_MDC G1
ETH1_MDIO J1
ETH1_TXCK F24
ETH1_TXCTL F15
ETH1_RXCK D8
ETH1_RXCTL F18
ETH1_TXD0 H27
ETH1_TXD1 D24
ETH1_TXD2 H18
ETH1_TXD3 D15
ETH1_RXD0 K8
ETH1_RXD1 F8
ETH1_RXD2 H8
ETH1_RXD3 C2

SD Card Connector (J24)

The SD Card interface comes from the HPS MUX pins which are powered by a 1.8V rail. The SD_DETECT is implemented using a GPIO. All pins, except SD_DETECT, go through a level translator between the SoC FPGA 1.8V rail to the connector's 3.3V rail.

Signal Name FPGA Ball
SD_CLK D132
SD_CMD AB132
SD_DETECT P124
SD_DAT0 E135
SD_DAT1 F132
SD_DAT2 AA135
SD_DAT3 V127

PCIex4 Edge Connector (J1)

The PCIe on the AXE5-Eagle is implemented as x4 Gen4 endpoint. The Agilex-5 is capable of supporting root port as well. The transceivers driving the data bus are powered by a 1.0V rail.

There is a differential 100MHz signal provided to the SoC FPGA related to the IP needs.

Signal Name FPGA Ball Signal Type
PCIE_100M_CK_P AY120 Clock Generator(1.8V)
PCIE_100M_CK_N AY115 Clock Generator (1.8V)

J1 Edge Connector:

Signal Name FPGA Ball Signal Type
PCIE_RSTb CF132 GPIO (3.3V)
PCIE_R_WAKE D34 GPIO (3.3V)
PCIE_CLK_P AV120 J1
PCIE_CLK_N AV115 J1
PET0_P GTSL1B_RX_CH0P (BD135) J1
PET0_N GTSL1B_RX_CH0N (BD133) J1
PET1_P GTSL1B_RX_CH1P (BB135) J1
PET1_N GTSL1B_RX_CH1N (BB133) J1
PET2_P GTSL1B_RX_CH2N (AY135)* J1
PET2_N GTSL1B_RX_CH2P (AY133)* J1
PET3_P GTSL1B_RX_CH3P (AV135) J1
PET3_N GTSL1B_RX_CH3N (AV133) J1
PER0_P GTSL1B_TX_CH0P (BE129) J1
PER0_N GTSL1B_TX_CH0N (BE126) J1
PER1_P GTSL1B_TX_CH1P (BC129) J1
PER1_N GTSL1B_TX_CH1N (BC126) J1
PER2_P GTSL1B_TX_CH2P (BA129) J1
PER2_N GTSL1B_TX_CH2N (BA126) J1
PER3_P GTSL1B_TX_CH3P (AW129) J1
PER3_N GTSL1B_TX_CH3N (AW126) J1

* Must be assigned this way for Quartus to pass. The PCIe takes care of the reversal

USB Type-A

The Quad-USB Type A connectors are driven from a Microchip 4-port USB HUB (USB5734T). This HUB interfaces to the SoC FPGA via USB ULP PHY (USB3320C) and a PIPE3 interfaces.

The ULPI signals are connected to the HPS MUX and the PIPE3 is connected to transceiver L1C_CH1

USB interface signals:

Signal Name FPGA Ball
USB_STP L135
USB_NXT AD134
USB_DIR J135
USB_CLK P132
USB_RST B134
USB_DATA0 AD135
USB_DATA1 M132
USB_DATA2 K132
USB_DATA3 AG129
USB_DATA4 J134
USB_DATA5 AG120
USB_DATA6 G134
USB_DATA7 G135
USB_SSTX_P GTSL1C_TX_CH2P (AN129)
USB_SSTX_N GTSL1C_TX_CH2N (AN126)
USB_SSRX_P GTSL1C_RX_CH2P (AM135)
USB_SSRX_N GTSL1C_RX_CH2N (AM133)

Micro USB (UART) Connector (J5)

J5 is connected to UART0 of the HPS MUX via an FTDI USB to UART bridge device (FT234XD).

Signal Name FPGA Ball
UART0_TX W134
UART0_RX AK115

Debug UART Connector (J34)

The 10-pin JTAG header provides a UART COM port into the FPGA fabric via the Arrow USB Blaster. These pins are connected to a 1.8V bank.

Signal Name FPGA Ball
DBG_TXD BK22
DBG_RXD CH4

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