AXE5 Eagle connector pinout - ArrowElectronics/Agilex-5 GitHub Wiki
AXE5-Eagle Connector Pin Assignments
FMC+ Connector
The FMC+ is a High Serial Pin Connector (HSPC) with 560 pins arranged in a 14x40 array. Only the colored signal boxes listed in the diagram below are connected to the Agilex 5.
A mezzanine board with an FMC HSPC (red region) can be used if the user doesn't need the signals in column L.
The connector image and a tabular pin assignment are shown below:
FMC+ (J3) Pinout
Note: The LA00-LA33 pins are connected to an HSIO bank on the Agilex-5. This bank can only be powered by a 1.2V or 1.3V power source. If using the LA00-LA33 pins as differential pairs, the VCCIO must be set to 1.3V via a DIP switch S10. For 1.3V, The FMC_ADJ_SEL DIP switch should be in the ON position as shown below.
SFP+ Connector
There are 2x SFP+ connectors on the AXE5-Eagle board and they are both connected to the same IO bank on the SoC FPGA. However, an HSIO bank can support only 1x 10Gb Ethernet Hard IP per bank. This means that if the user needs to use both 10Gb Ethernet ports, one will have to use a Soft IP.
The SFP+ control signals go through a 1.2V to 3.3V level translator between the SoC FPGA and the connector. Similarly, the MUX_I2C signals go through a 1.8V to 3.3V level translation through the I2C MUX.
| SFPA Signal | FPGA Ball | VCCIO |
|---|---|---|
| SFPA_TX_DIS | Y77 | 1.2V |
| SFPA_TX_FAULT | Y74 | 1.2V |
| SFPA_RS1 | Y58 | 1.2V |
| SFPA_RS0 | AC64 | 1.2V |
| SFPA_LOS | AG64 | 1.2V |
| SFPA_M-DEF0 | A80 | 1.2V |
| SFPA_SDA* | MUX_I2C_SDA (F4) | 1.8V |
| SFPA_SCL* | MUX_I2C_SCL (D4) | 1.8V |
| SFPA_TD_P | GTSL1C_TX_CH0P (AU129) | |
| SFPA_TD_N | GTSL1C_TX_CH0N (AU126) | |
| SFPA_RD_P | GTSL1C_RX_CH0P (AT135) | |
| SFPA_RD_N | GTSL1C_RX_CH0N (AT133) |
| SFPB Signal | FPGA Ball | VCCIO |
|---|---|---|
| SFPB_TX_DIS | AC50 | 1.2V |
| SFPB_TX_FAULT | Y55 | 1.2V |
| SFPB_RS1 | AC53 | 1.2V |
| SFPB_RS0 | AG57 | 1.2V |
| SFPB_LOS | AC61 | 1.2V |
| SFPB_M-DEF0 | AG83 | 1.2V |
| SFPB_SDA* | MUX_I2C_SDA (F4) | 1.8V |
| SFPB_SCL* | MUX_I2C_SCL (D4) | 1.8V |
| SFPB_TD_P | GTSL1C_TX_CH3P (AL129) | |
| SFPB_TD_N | GTSL1C_TX_CH3N (AL126) | |
| SFPB_RD_P | GTSL1C_RX_CH3P (AK135) | |
| SFPB_RD_N | GTSL1C_RX_CH3N (AK133) |
*Note: The user must set up the TCA9544A I2C MUX to select the appropriate SFP+ port to communicate with.
HDMI Output
The HDMI connector (J11) is driven by an Analog Device ADV7511W HDMI Transmitter device. The ADV7511W is driven from the SoC FPGA with a parallel 24-bit bus and control signals described in the table below. All signals are driven from HVIO banks powered at 1.8V.
The HDMI I2C signals are driven by the I2C MUX (see TCA9544A above).
| HDMI Signal | FPGA Ball |
|---|---|
| HDMI_I2C_SCL | MUX_I2C_SCL (D4) |
| HDMI_I2C_SDA | MUX_I2C_SDA (F4) |
| CEC_CLK | BF25 |
| CT_HPD | BW19 |
| HDMI_CLK | BK31 |
| HDMI_HS | CF12 |
| HDMI_VS | BH19 |
| HDMI_DE | BK19 |
| HDMI_INT | BF16 |
| HDMI_D0 | BF32 |
| HDMI_D1 | CH12 |
| HDMI_D2 | BM22 |
| HDMI_D3 | BF21 |
| HDMI_D4 | BE21 |
| HDMI_D5 | BP22 |
| HDMI_D6 | BR22 |
| HDMI_D7 | BE25 |
| HDMI_D8 | BU22 |
| HDMI_D9 | BW28 |
| HDMI_D10 | BU28 |
| HDMI_D11 | BM31 |
| HDMI_D12 | BR28 |
| HDMI_D13 | BM28 |
| HDMI_D14 | BK28 |
| HDMI_D15 | BH28 |
| HDMI_D16 | BF36 |
| HDMI_D17 | BE43 |
| HDMI_D18 | BU31 |
| HDMI_D19 | BP31 |
| HDMI_D20 | BR31 |
| HDMI_D21 | BF29 |
| HDMI_D22 | BF40 |
| HDMI_D23 | BE29 |
RJ-45 Connectors (J4 and J28)
There are 2 RJ-45 Ethernet connectors on the AXE5-Eagle board which are driven by ADIN1300 Ethernet PHY devices. Each of the PHY devices is driven by the RGMII signals described below.
The RJ45 (J4) is driven from the HPS EMAC2 connected to the HPS MUX and driven at 1.8V logic levels.
| Signal Name | FPGA Ball |
|---|---|
| ETH_RST | T124 |
| ETH_MDC | Y132 |
| ETH_MDIO | T127 |
| ETH_TXCK | M127 |
| ETH_TXCTL | K127 |
| ETH_RXCK | M124 |
| ETH_RXCTL | AB127 |
| ETH_TXD0 | K124 |
| ETH_TXD1 | Y127 |
| ETH_TXD2 | F127 |
| ETH_TXD3 | Y124 |
| ETH_RXD0 | H127 |
| ETH_RXD1 | AB124 |
| ETH_RXD2 | F124 |
| ETH_RXD3 | D124 |
The RJ45 (J28) is driven from the FPGA Fabric with HVIO powered by a 1.8V voltage source. This can be driven by HPS EMAC0 (through the FPGA fabric) or by an Ethernet Triple Speed Ethernet (TSE) IP in the FPGA.
The interface to the HPS EMAC0 requires that the ETH1_RXCK and ETH1_RXD1 pins are swapped. This is implemented in the AXE5-Eagle-ES release. HPS EMAC0 functionality will not be available with the AXE5-Eagle-ES0 release.
| Signal Name | FPGA Ball |
|---|---|
| ETH1_RST | F27 |
| ETH1_MDC | G1 |
| ETH1_MDIO | J1 |
| ETH1_TXCK | F24 |
| ETH1_TXCTL | F15 |
| ETH1_RXCK | D8 |
| ETH1_RXCTL | F18 |
| ETH1_TXD0 | H27 |
| ETH1_TXD1 | D24 |
| ETH1_TXD2 | H18 |
| ETH1_TXD3 | D15 |
| ETH1_RXD0 | K8 |
| ETH1_RXD1 | F8 |
| ETH1_RXD2 | H8 |
| ETH1_RXD3 | C2 |
SD Card Connector (J24)
The SD Card interface comes from the HPS MUX pins which are powered by a 1.8V rail. The SD_DETECT is implemented using a GPIO. All pins, except SD_DETECT, go through a level translator between the SoC FPGA 1.8V rail to the connector's 3.3V rail.
| Signal Name | FPGA Ball |
|---|---|
| SD_CLK | D132 |
| SD_CMD | AB132 |
| SD_DETECT | P124 |
| SD_DAT0 | E135 |
| SD_DAT1 | F132 |
| SD_DAT2 | AA135 |
| SD_DAT3 | V127 |
PCIex4 Edge Connector (J1)
The PCIe on the AXE5-Eagle is implemented as x4 Gen4 endpoint. The Agilex-5 is capable of supporting root port as well. The transceivers driving the data bus are powered by a 1.0V rail.
There is a differential 100MHz signal provided to the SoC FPGA related to the IP needs.
| Signal Name | FPGA Ball | Signal Type |
|---|---|---|
| PCIE_100M_CK_P | AY120 | Clock Generator(1.8V) |
| PCIE_100M_CK_N | AY115 | Clock Generator (1.8V) |
J1 Edge Connector:
| Signal Name | FPGA Ball | Signal Type |
|---|---|---|
| PCIE_RSTb | CF132 | GPIO (3.3V) |
| PCIE_R_WAKE | D34 | GPIO (3.3V) |
| PCIE_CLK_P | AV120 | J1 |
| PCIE_CLK_N | AV115 | J1 |
| PET0_P | GTSL1B_RX_CH0P (BD135) | J1 |
| PET0_N | GTSL1B_RX_CH0N (BD133) | J1 |
| PET1_P | GTSL1B_RX_CH1P (BB135) | J1 |
| PET1_N | GTSL1B_RX_CH1N (BB133) | J1 |
| PET2_P | GTSL1B_RX_CH2N (AY135)* | J1 |
| PET2_N | GTSL1B_RX_CH2P (AY133)* | J1 |
| PET3_P | GTSL1B_RX_CH3P (AV135) | J1 |
| PET3_N | GTSL1B_RX_CH3N (AV133) | J1 |
| PER0_P | GTSL1B_TX_CH0P (BE129) | J1 |
| PER0_N | GTSL1B_TX_CH0N (BE126) | J1 |
| PER1_P | GTSL1B_TX_CH1P (BC129) | J1 |
| PER1_N | GTSL1B_TX_CH1N (BC126) | J1 |
| PER2_P | GTSL1B_TX_CH2P (BA129) | J1 |
| PER2_N | GTSL1B_TX_CH2N (BA126) | J1 |
| PER3_P | GTSL1B_TX_CH3P (AW129) | J1 |
| PER3_N | GTSL1B_TX_CH3N (AW126) | J1 |
* Must be assigned this way for Quartus to pass. The PCIe takes care of the reversal
USB Type-A
The Quad-USB Type A connectors are driven from a Microchip 4-port USB HUB (USB5734T). This HUB interfaces to the SoC FPGA via USB ULP PHY (USB3320C) and a PIPE3 interfaces.
The ULPI signals are connected to the HPS MUX and the PIPE3 is connected to transceiver L1C_CH1
USB interface signals:
| Signal Name | FPGA Ball |
|---|---|
| USB_STP | L135 |
| USB_NXT | AD134 |
| USB_DIR | J135 |
| USB_CLK | P132 |
| USB_RST | B134 |
| USB_DATA0 | AD135 |
| USB_DATA1 | M132 |
| USB_DATA2 | K132 |
| USB_DATA3 | AG129 |
| USB_DATA4 | J134 |
| USB_DATA5 | AG120 |
| USB_DATA6 | G134 |
| USB_DATA7 | G135 |
| USB_SSTX_P | GTSL1C_TX_CH2P (AN129) |
| USB_SSTX_N | GTSL1C_TX_CH2N (AN126) |
| USB_SSRX_P | GTSL1C_RX_CH2P (AM135) |
| USB_SSRX_N | GTSL1C_RX_CH2N (AM133) |
Micro USB (UART) Connector (J5)
J5 is connected to UART0 of the HPS MUX via an FTDI USB to UART bridge device (FT234XD).
| Signal Name | FPGA Ball |
|---|---|
| UART0_TX | W134 |
| UART0_RX | AK115 |
Debug UART Connector (J34)
The 10-pin JTAG header provides a UART COM port into the FPGA fabric via the Arrow USB Blaster. These pins are connected to a 1.8V bank.
| Signal Name | FPGA Ball |
|---|---|
| DBG_TXD | BK22 |
| DBG_RXD | CH4 |
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