AXE5 Eagle block diagrams - ArrowElectronics/Agilex-5 GitHub Wiki

AXE5-Eagle Block Diagram

The AXE5-Eagle board contains an SoC FPGA device and many peripheral devices.



Top Board View Place Holder



Intel Agilex 5 E-Series SoC

The initial release of boards will have the Engineering Silicon SoC with a density of 656KLE. When the Production 434KLE device comes out, the board will be shipped with an A5ED043BB32AE4S SoC FPGA.

  • HPS:
    • Dual ARM® A55 and Dual ARM® A76 CPUs
    • Up to 1.5 GHz max clock speed
    • Cortex-A55: 1.333 GHz, 32 KB L1, 128KB L2 Cache
    • Cortex-A76: 1.6 GHz, 64KB L1, 256KB L2 Cache
    • 2 MB shared L3 Cache
    • 48 Dedicated HPS I/O pins
    • 4 Hard Memory Controllers (LPDDR4, DDR4, LPDDR5)
  • FPGA Fabric:
    • 656,080 Logic Elements (LE)
    • 1,611 (31.46Mb) M20K Memory
    • 11,120 (6.79Mb) MLAB Memory
    • 1,692 18x19 Multipliers
    • 120 HVIO (1.8V - 3.3V) I/O pins
    • 384 HSIO (1.05V - 1.3V) I/O pins
    • 4 Hard Memory Controllers (LPDDR4, LPDDR5, DDR4), x32
    • 28 MIPI D-PHY channels
    • 24x 17.1Gbps Transceivers
    • 6x PCIe Gen4 Hard blocks
    • 6x 10Gb EMAC Hard IP blocks
    • 2nd generation Intel Hyperflex Core architecture

FPGA LPDDR4
HPS LPDDR4
FMC+ Connector
CRUVI HS
CRUVI LS
microSD Card Connector
ADIN1300 Ethernet PHY
RJ-45 Ethernet Connector
USB PHY
USB HUB
dual USB-A Connector
ADV7511W HDMI Transmitter
HDMI Connector
micro-USB to UART Connector
HPS 2x Push Button
FPGA 2x Push Button
HPS LEDs
4x FPGA RGB LEDs
HPS 2x DIP Switch
FPGA 2x DIP Switch
12 VDC Power Jack
Si5332A Programmable Clock Generator
QSPI for Configuration (back side)
10Gb SFP+ cage
AD5592R 8-ch ADC/DAC
PCIe Gen4 x4 Edge Connector
2x Temperature Sensors (back side)
EEPROM
MAX31760 Fan-speed Controller



Return - AXE5-Eagle Development Platform
Return - Developer Resources Page

⚠️ **GitHub.com Fallback** ⚠️