AXE5 Eagle GHRD create hps - ArrowElectronics/Agilex-5 GitHub Wiki

In this step, we create the Processor sub-system and add to it the previously created diaplat and peripheral sub-systems.

• Open Platform Designer from Quartus Prime via one of the two methods below:

  • Tools -> Platform Designer menu, or
  • Click on its icon in the tool bar.  An Open System window opens where you specify the name of the Platform Designer System.
  • Click this icon on the Platform Designer system selection and name it ghrd_hps_system and click Create. Click Create again in the Open System Window.

• After the Create New System Completed window is done successfully, click Close.

• Remove the _clock_in IP from the System View, and answer Yes.

Expand the Processors and Peripherals -> Hard Processor Systems and double-click Hard Processor System Intel Agilex 5 FPGA IP to add it to the system.

The HPS peripherals used in the GHRD are:

• Via the 48-pin HPS MUX pins:
  • UART0, I2C0, GPIOA[11:6], USB1, SDMMC (as SD Card), EMAC2+MDIO2.
• Via the FPGA fabric pins:
  • EMAC0+MDIO0, I2C1, SPIM0, GPIOB[11,10,4].

This action opens the HPS configuration window.

• In the FPGA Interfaces tab,
  • un-check all boxes in the General section.
  • In the FPGA to HPS Subordinate section, change settings to:
    • set Interface Specification to AXI-4
    • set Enable/Data Width to 256-bit
    • set Interface Address Width to 31-bit 2GB
  • In the FPGA to SDRAM Subordinate section, change settings to:
    • set Enable/Data Width to to 64-bit
    • set Interface Address Width to 32-bit 4GB
  • In the HPS to FPGA Manager section, change settings to:
    • set Enable/Data Width to to 32-bit
    • set Interface Address Width to 32-bit 4GB
  • In the Lightweight HPS to FPGA Manager section, change settings to:
    • set Enable/Data Width to to 32-bit
    • set Interface Address Width to 29-bit 512MB
  • In the DMA Peripheral Request section, leave all setting at the default No.
  • In the Interrupts section, check the box to Enable FPGA-to-HPS interrupts.

• Select the SDRAM tab,
  • Check the box Enable EMIF INIU AXI Interface
  • Set the EMIF Topology to 1x32 bit
  • Click Finish.

• Skip to selecting the Pin Mux and Peripherals tab,
  • In the Advanced IP Placement sub-tab. make the following selections:
    • HPS_IOA_1 to HCLK:HPS_OSC_CLK
    • HPS_IOA_2 to NONE
    • HPS_IOA_3 to UART0:TX
    • HPS_IOA_4 to UART0:RX
    • HPS_IOA_5 to I2C0:SDA
    • HPS_IOA_6 to I2C0:SCL
    • HPS_IOA_7 to GPIO0:IO6
    • HPS_IOA_8 to GPIO0:IO7
    • HPS_IOA_9 to GPIO0:IO8
    • HPS_IOA_10 to GPIO0:IO9
    • HPS_IOA_11 to GPIO0:IO10
    • HPS_IOA_12 to GPIO0:IO11
    • HPS_IOA_13 to USB1:CLK
    • HPS_IOA_14 to USB1:STP
    • HPS_IOA_15 to USB1:DIR
    • HPS_IOA_16 to USB1:DATA0
    • HPS_IOA_17 to USB1:DATA1
    • HPS_IOA_18 to USB1:NXT
    • HPS_IOA_19 to USB1:DATA2
    • HPS_IOA_20 to USB1:DATA3
    • HPS_IOA_21 to USB1:DATA4
    • HPS_IOA_22 to USB1:DATA5
    • HPS_IOA_23 to USB1:DATA6
    • HPS_IOA_24 to USB1:DATA7
    • HPS_IOB_1 to SDMMC:DATA0
    • HPS_IOB_2 to SDMMC:DATA1
    • HPS_IOB_3 to SDMMC:CCLK
    • HPS_IOB_4 to NONE
    • HPS_IOB_5 to GPIO1:IO4
    • HPS_IOB_6 to SDMMC:DATA2
    • HPS_IOB_7 to SDMMC:DATA3
    • HPS_IOB_8 to SDMMC:CMD
    • HPS_IOB_9 to MDIO2:MDIO
    • HPS_IOB_10 to MDIO2:MDC
    • HPS_IOB_11 to GPIO1:IO10
    • HPS_IOB_12 to GPIO1:IO11
    • HPS_IOB_13 to EMAC2:TX_CLK
    • HPS_IOB_14 to EMAC2:TX_CTL
    • HPS_IOB_15 to EMAC2:RX_CLK
    • HPS_IOB_16 to EMAC2:RX_CTL
    • HPS_IOB_17 to EMAC2:TXD0
    • HPS_IOB_18 to EMAC2:TXD1
    • HPS_IOB_19 to EMAC2:RXD0
    • HPS_IOB_20 to EMAC2:RXD1
    • HPS_IOB_21 to EMAC2:TXD2
    • HPS_IOB_22 to EMAC2:TXD3
    • HPS_IOB_23 to EMAC2:RXD2
    • HPS_IOB_24 to EMAC2:RXD3
    • Click Apply Selections.

• Select the Advanced FPGA Placement sub-tab. make the following selections:
  • EMAC 0 to Yes
  • I2C 1 to Yes
  • SPIM 0 to Yes
  • EMAC 0 Interface to GMII, EMAC 0 PHY to MDIO
  • EMAC 1 Interface to MII, EMAC 1 PHY to None
  • Click Apply Selections

• Select the HPS Clocks, Resets, Power tab,
  • In the Input Clocks sub-tab, keep all defaults.

• Select the PLL Clocks sub-tab,
  • In the Peripheral Clocks section,
    • set EMAC 0 Clock Frequency Select to 250 Mhz
    • set EMAC 2 Clock Frequency Select to 250 Mhz
  • In the HPS-to-FPGA User Clocks section,
    • check the boxes to enable User 0 and User 1 clocks
    • set the H2F User0 Clock Source Selects to MainC1 with a frequency of 250.0 MHz
    • set the H2F User1 Clock Source Selects to MainC1 with a frequency of 100.0 MHz

• Select the Power & Reset sub-tab,
  • check all boxes except Enable Watchdog Reset

• Click Finish.
• Rename the HPS module as agilex_5_soc.
• Rename the exported reset_in/in_reset to sys_reset,
• Connect the h2f_user1_clk to the hps2fpga_axi_clock, lwhps2fpga_axi_clock, f2sdram_axi_clock, fpga2hps_clock, and the reset_in/clk,
• Connect the h2f_user0_clk to the emac_timestamp_clk and emac_ptp_clk,
• Connect the reset_in/out_reset port to the agilex_5_soc's hps2fpga_axi_reset, lwhps2fpga_axi_reset, f2sdram_axi_reset, fpga2hps_reset ports.
• Connect the emif0_ch0_axi_clk and emif0_csr_axi_clk ports to the h2f_user1_clk spine,
• Connect the emif0_ch0_axi_rst and emif0_csr_axi_rst ports to the reset_in/in_reset spine,

• Export the agilx-5_soc/emac0_mdio port as _emac0_mdio,
• Export the agilx-5_soc/emac0_app_rst port as _emac0_app_rst,
• Export the agilx-5_soc/emac0 port as _emac0,
• Export the agilx-5_soc/emac2_app_rst port as _emac2_app_rst,
• Export the agilx-5_soc/spim0 port as _spim0,
• Export the agilx-5_soc/spim0_sclk_out port as _spim0_sclk_out,
• Export the agilx-5_soc/I2C1_scl_i port as _i2c1_scl_i,
• Export the agilx-5_soc/I2C1_scl_oe port as _i2c1_scl_oe,
• Export the agilx-5_soc/I2C1 port as _i2c1,
• Export the agilx-5_soc/hps_io port as _hps_io,
• Export the agilx-5_soc/usb31_io port as _usb_31_io,

• Type emif in the IP Catalog search bar and find the __External Memory Interface (EMIF) IP**,
• Double click it to add it to the System Contents.
• In the wizard, make the following settings:
  • Uncheck the Technology Generation box and set it to LPDDR4,
  • Set the Device DQ Width to 16,
  • Make sure the Memory Preset has the LPDDR4-2667 CL24 Single-Component 1R 1CPR 16GB is selected -Click Finish

• Rename it emif_bank3a,

• Export the ref_clk_0 port as bank3a_lpddr3_refclk,

• Export mem_0 port as bank3a_lpddr4,

• Export oct_0 port as bank3a_lpddr4_oct,

• Connect core_init_n_0 port to agilex_5_soc/h2f_reset port,

• Connect usr_async_clk_0 port to agilex_5_soc/h2f_user1_clk spine,

• Connect s0_axi port to agilex_5_soc/emif0_ch0_axi port,

• Connect s0_axil_clk port to agilex_5_soc/h2f_user1_clk spine,

• Connect s0_axil_rst_n port to agilex_5_soc/h2f_reset port,

• Connect s0_axil port to agilex_5_soc/emif0_csr_axi port,

The SRAM is added to the AXI-Lite interface.

• Type onchip in the IP Catalog search bar and find the __On-Chip Memory II (RAM or ROM) Intel FPGA IP**,
• Double click it to add it to the System Contents.
• In the wizard, make the following settings:
  • Set Interface type to AXI-4,
  • Set Block type to M20K,
  • Set S1 Data width to 32,
  • Set S1 AXI Transaction ID Width to 7,
  • Set Total memory size to 32768,
  • Uncheck the Initialize memory content.

• Click Finish.
• Rename it onchip_sram.
• Connect its clk1 port to the agilex_5_soc/h2f_user0_clk port,
• Connect its reset1 port to the reset_in/out_reset port,
• Connect its axi_s1 port to the agilex_5_soc/lwhps2fpga port.

• In the IP Catalog, expand the system category,

• Double-click the peripheral_sys and click Finish to add it to the System Contents. Rename it peripheral_sys.
• Double-click the video_sys and click Finish to add it to the System Contents. Rename it video_sys.

• Connect the h2f_user1_clk to the peripheral_sys/clk and the video_sys/clk,
• Connect the reset_in/out_reset port to the peripheral_sys/reset and video_sys_reset ports.
• Connect the peripheral_sys' dipsw_irq, jtag_uart_irq, and button_irq ports to the agilex_5_soc/fpga2hps_interrupt port.
• Connect the video_sys/hdmi_dmac port to the agilex_5_soc/fpga2hps_interrupt port.
• Connect the video_sys/mm_video_bridge_s0 port to the agilex_5_soc/lwhps2fpga port.
• Connect the video_sys/hdmi_dmac_master port to the agilex_5_soc/f2sdram port.

• Type jtag in the IP Catalog search bar and find the JTAG to Avalon Master Bridge Intel FPGA IP IP,
• Double-click it and click Finish to add it to the System Contents.
• Rename it fpga_only_master,
• Connect its clk port to the agilex_5_soc/h2f_user1_clk spine,
• Connect its reset port to the reset_in/out_reset spine,
• Connect its master port to the onchip_sram/axi_s1 and peripheral_sys/mm_peripheral_bridge_s0 ports,
• Connect its master_reset port to its clk_reset port

• Type jtag in the IP Catalog search bar and find the JTAG to Avalon Master Bridge Intel FPGA IP IP,
• Double-click it and click Finish to add it to the System Contents.
• Rename it f2sdram_only_master,
• Connect its clk port to the agilex_5_soc/h2f_user1_clk spine,
• Connect its reset port to the reset_in/out_reset spine,
• Connect its master port to the agilex_5_soc/f2sdram port

The CPU address map need to me assigned to the various peripherals.

• Click on the menu System --> Assign Base Addresses

• Right-click on the video_sys and Drill into Subsystem_

  • Perform System --> Assign Base Addresses
  • Return to ghrd_hps_system.

• Right-click on the peripheral_sys and Drill into Subsystem_

  • Perform System --> Assign Base Addresses
  • Return to ghrd_hps_system.

• With no errors in the System Messages window, click the Generate HDL button in the lower right corner of Platform Designer,

  • Click the Generate button.
  • Click Yes at the Save Changes pop-up
  • Click Close in the Generate Completed window.

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Next - Create Top-Level Design
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