AXE5 Eagle GHRD adding other peripherals - ArrowElectronics/Agilex-5 GitHub Wiki

Other peripherals which the user may find useful are added and the finishing touches are done to the Platform Designer build.

Add Avalon Memory Mapped Pipeline Bridge
Add System ID Peripheral
Add JTAG UART
Add Push Button IP
Add DIP Switch IP
Add RGB LED0 IP
Assign Base Addresses

  • Open Platform Designer from Quartus Prime via one of the two methods below:

    • Tools -> Platform Designer menu, or
    • Click on its icon in the tool bar.  An Open System window opens where you specify the name of the Platform Designer System.
    • Click this icon on the Platform Designer system selection and name it peripheral_sys and click Create. Click Create again in the Open System Window.
  • After the Create New System Completed window is done successfully, click Close.

Add Avalon Memory Mapped Pipeline Bridge IP

  • Find the IP in the IP Catalog by typing **pipeline bridge" in the search field.
  • Double-click it to add it to the System Contents.
  • In the wizard, change the Address width parameter to 24.
  • Click Finish.
  • Right-click mm_bridge_0 and select Rename to mm_bridge
  • Connect its clk port to clock_in/out_clk spine.
  • Connect its reset port to the reset_in/out_reset spine.
  • Export its s0 bus as mm_peripheral_bridge_s0

Add the System ID Peripheral IP

  • Find the System ID Peripheral Intel FPGA IP in the IP Catalog.
  • Double-click it to add it to the System Contents.
  • In the wizard, change the 32 bit System ID parameter to 0xa5e065be
  • Click Finish.
  • Right-click sysid_qsys_0 and select Rename to sys_id.
  • Connect its clk port to clock_in/out_clk spine,
  • Connect its reset port to the reset_in/out_reset spine.
  • Connect its control_slave port to mm_bridge/m0 port

Add JTAG UART IP

  • Find the JTAG UART Intel FPGA IP in the IP Catalog.
  • Double-click it to add it to the System Contents.
  • Click Finish.
  • Rename it jtag_uart.
  • Connect its clk port to clock_in/out_clk spine,
  • Connect its reset port to the reset_in/out_reset spine.
  • Connect its avalon_jtag_slave port to mm_bridge/m0 spine.
  • Export its irq port as jtag_uart_irq.

Add Push Button IP

  • Find the PIO (Parallel I/O) Intel FPGA IP in the IP Catalog.
  • Double-click it to add it to the System Contents.
  • Set the Width to 2 and the Direction to Input,
  • Check the Synchronously capture and Enable bit-clearing boxes in the Edge capture register section and set the Edge Type to FALLING,
  • Check the Generate IRQ box and set the IRQ Type to EDGE
  • Click Finish.
  • Rename it button_pio.
  • Connect its clk port to clock_in/out_clk spine,
  • Connect its reset port to the reset_in/out_reset spine.
  • Connect its s1 port to mm_bridge/m0 spine.
  • Export its irq port as button_irq.
  • Export its external_connections as push_button.

Add DIP Switch IP

  • Find the PIO (Parallel I/O) Intel FPGA IP in the IP Catalog.
  • Double-click it to add it to the System Contents.
  • Set the Width to 2 and the Direction to Input,
  • Check the Synchronously capture and Enable bit-clearing boxes in the Edge capture register section and set the Edge Type to ANY,
  • Check the Generate IRQ box and set the IRQ Type to EDGE
  • Click Finish.
  • Rename it dipsw_pio.
  • Connect its clk port to clock_in/out_clk spine,
  • Connect its reset port to the reset_in/out_reset spine.
  • Connect its s1 port to mm_bridge/m0 spine.
  • Export its irq port as dipsw_irq.
  • Export its external_connections as dipsw.

Add RGB LED0 IP

  • Find the PIO (Parallel I/O) Intel FPGA IP in the IP Catalog.
  • Double-click it to add it to the System Contents.
  • Set the Width to 3 and the Direction to Output
  • Click Finish.
  • Rename it rgb_led0.
  • Connect its clk port to clock_in/out_clk spine,
  • Connect its reset port to the reset_in/out_reset spine.
  • Connect its s1 port to mm_bridge/m0 spine.
  • Export its external_connections as rgb_led0.

Assign Base Addresses

Normally, IP base addresses are assigned in Platform Designer by clicking the menu bar, selecting System -> Assign Base Addresses. BUT in this case, we need to assign the base addresses manually and lock them because the Linux device tree is expecting them to be assigned at specific addresses. To do this double-click the address in the Base column, modify it per the table below, then click the open lock icon to the left of it to lock and prevent the system from modifying the address. Note: The end address is automatically recalculated and updated by the system.

Interrupt and their numbers, for each IP block, will be assigned at the higher level with the HPS instantiated.

Port Base Address
rgb_led0 0x0000_0000
dipsw_pio 0x0000_0010
button_pio 0x0000_0020
sys_id 0x0000_0030
jtag_uart 0x0000_0038

Conclude settings in Platform Designer

  • Save the peripheral_sys.qsys using File --> Save, Close, then exit Platform Designer.

When asked to Generate Now?, click No.

Next - Creating Processor System
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