AXE5 Eagle GHRD add display - ArrowElectronics/Agilex-5 GitHub Wiki

Add Video IP

This design uses the Analog Devices® AXI_HDMI_TX IP core to implement the HDMI interface to the display monitor.

The HDMI interface requires multiple IP cores from the IP Catalog

Open Platform Designer from Quartus Prime via one of the two methods below:
- Tools -> Platform Designer menu, or
- Click on its icon in the tool bar. An Open System window opens where you specify the name of the Platform Designer System.
- Click this icon on the Platform Designer system selection and name it video_sys and click Create. Click Create again in the Open System Window.

After the Create New System Completed window is done successfully, click Close.

type avalon memory in the IP Catalog search bar and find the Avalon Memory Mapped Pipeline Bridge Intel FPGA IP,
Double click it to add it to the System Contents.
In the wizard, make the following settings:
- In the Address section, set the Address Width to 24,
- Leave all other setting to their defaults.
- Click Finish.

Right-click the mm_bridge_0 and select Rename. Change name to mm_video_bridge.
Double-click in the Export the column to export the s0 as mm_video_bridge_s0.
Connect its clk port to clock_in/out_clk port,
Connect its reset port to reset_in/out_reset port,

type pll in the IP Catalog search bar and find the IOPLL Intel FPGA IP,
Double-click it to add it to the System Contents.
In the wizard, make the following settings:
- In the General tab, insure the Reference Clock Frequency is set to 50.0 MHz,
- Un-check the Enable locked output port,
- Change the outclk0 Desired Frequency to 148.5 MHz,
- Click Finish.

Rename it in the System Contents tab to hdmi_pll by right-click the name -> Rename,
Connect its reset port to the reset_in/out_reset spine,
Double-click in the Export the column to export the refclk as hdmi_pll_refclk.

Type axi_dmac in the IP Catalog search bar to find it in the Analog Devices Library,
Double-click it to add it to the System Contents,
In the wizard, make the following settings then click Finish:
- Change the Source Type to Memory-Mapped AXI
- Change the Destination Type to Streaming AXI
- Check the Features boxes for Cyclic Transfer Support and 2D Transfer Support,
- Check the AXI Stream interface common configuration box for AXI Stream interface has TLAST
- Click Finish.

Rename it in the System Contents tab to hdmi_dmac by right clicking the name -> Rename,
Connect its s_axi_clock, m_src_axi_clock, and if_m_axis_aclk ports to the clock_in/out_clk spine.
Connect its s_axi_reset, and m_src_axi_reset ports to the reset_in/out_reset spine.
Connect its s_axi bus to the mm_video_bridge/m0 port.
Double-click in the Export the column to export the interrupt_sender port as hdmi_dmac port.
Double-click in the Export the column to export the m_src_axi bus as hdmi_dmac_master bus.

Type axi_hdmi_tx in the IP Catalog search bar to find it in the Analog Devices Library,
Double-click it to add it to the System Contents,
Change the FPGA TECHNOLOGY to __Agilex-5 E-Series and keep all other default settings in the wizard, and Click Finish.

Rename it in the System Contents tab to axi_hdmi_tx.
Connect its s_axi_clock, and vdma_clock ports to the clock_in/out_clk spine.
Connect its s_axi_reset, and vdma_reset ports to the reset_in/out_reset spine.
Connect its vdma_if bus to the axi__dmac/m_axis bus.
Connect its s_axi bus to the mm_video_bridge/m0 bus.
Connect its hdmi_clock to the hdmi_pll/outclk0 port.
Double-click the Export column of the hdmi_if and name it hdmi.

Save the video_sys.qsys using File --> Save, Close, then exit Platform Designer.

When asked to Generate Now?, click No.