Terasic DE0‐Nano‐SoC Kit Atlas‐SoC Kit - ArrowElectronics/ADI-Powertree GitHub Wiki
The DE0-Nano-SoC development kit from Terasic presents a robust hardware design platform built around the Intel® System-on-Chip (SoC) FPGA, which combines the latest dual-core ARM® Cortex®-A9 embedded cores with industry-leading, programmable logic for ultimate design flexibility.
- FPGA Device
- Cyclone® V SE 5CSEMA4U23C6N device
- Serial configuration device
- USB-Blaster II on-board for programming; JTAG mode
- HPS (Hard Processor System)
- 925MHz dual-core ARM® Cortex®-A9 processor
- 1GB DDR3 SDRAM (32-bit data bus)
- 1Gb Ethernet PHY with RJ45 connector
Terasic DE0-Nano-SoC Kit/Atlas-SoC Kit
Power Tree for the Terasic DE0-Nano-SoC Kit/Atlas-SoC Kit
| Product | Description | Buy Now |
|---|---|---|
| LTC3612 | 3A, 4MHz Monolithic Synchronous Step-Down DC/DC Converter | Buy LTC3612 |
| LT3580 | Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization | Buy LT3580 |
| LT3080 | Adjustable 1.1A Single Resistor Low Dropout Regulator | Buy LT3080 |
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Utilizing pre-existing power management reference designs can provide a good starting point, but modifications are often necessary to meet specific performance and power requirements. Arrow Electronics engineers can assist in analyzing your requirements, identifying the necessary modifications, and ensuring that the final design achieves optimal performance and power efficiency. Their knowledge and experience in power management enable them to provide valuable guidance and support throughout the design process, helping you achieve the best possible power solution for your specific application. Download the “Analog Devices Power Trees for FPGAs and GPUs” Guide |