1: Intro - AmeerAbdelhadi/Multiported-RAM GitHub Wiki

Modular Multi-ported SRAM-based Memories

Ameer M. S. Abdelhadi and Guy G. F. Lemieux

The University of British Columbia (UBC) 2014

{ ameer.abdelhadi; guy.lemieux } @ gmail.com

A fully parameterized and generic Verilog implementation of the suggested modular multi-ported SRAM-based memories, together with previous approaches are provided as open source hardware. A run-in-batch flow manager to simulate and synthesize various designs with various parameters in batch using Altera's ModelSim and Quartus II is also provided.

LICENSE: BSD 3-Clause ("BSD New" or "BSD Simplified") license.

Please refer to the full paper for more information:

A. M.S. Abdelhadi and G. G.F. Lemieux, "Modular Multi-ported SRAM-based Memories," ACM/SIGDA Intl Symp. on Field-Programmable. Gate Arrays (FPGA 14), Feb. 2014. http://www.ece.ubc.ca/~lemieux/publications/abdelhadi-fpga2014.pdf