3: Directory Structure - AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM GitHub Wiki

  • README: This file!
  • LICENSE: BSD 3-Clause ("BSD New" or "BSD Simplified") license
  • fccm2015-paper.pdf: The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'2014) paper
  • fccm2015-slides.pdf: The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'2014) slides
  • altera.12.0.ubc.csh: C-shell script: Setup environment variables and Altera 12.0 CAD flow from The University of British Columbia (UBC)
  • altera.13.1.ubc.csh: C-shell script: Setup environment variables and Altera 13.1 CAD flow from The University of British Columbia (UBC)
  • altera.14.0.ubc.csh: C-shell script: Setup environment variables and Altera 14.0 CAD flow from The University of British Columbia (UBC)
  • sim: C-shell script: A run-in-batch simulation flow manager
  • syn: C-shell script: A run-in-batch synthesis flow manager
  • mux: C-shell script: Wide pipelined multiplexer generator
  • pe: C-shell script: Priority-encoder recursive generator
  • reduction: C-shell script: Wide pipelined reduction function generator
  • ii2dcam.qpf: Quartus II project file
  • ii2dcam.qsf: Quartus II settings file
  • ii2dcam.sdc: Synopsys design constraints file; Design constraints and timing assignments
  • config.vh: Verilog: Generated by 'syn', contains design parameters
  • utils.vh: Verilog: Design utilities (pre-compile macros)
  • bcam_bhv.v: Behavioral description of binary CAM
  • camctl.v: BCAM Controller
  • dpmlab.v: Altera's MLAB dual-port RAM
  • idxram.v: indices RAM
  • ii2dcam9b.v: An indirectly-indexed 2D BCAM (II2DCAM) stage of 9-bits pattern
  • ii2dcam_tb.v: indirectly-indexed 2D BCAM (II2DCAM) Testbench
  • ii2dcam.v: II2DCAM top hierarchy
  • iitram9b.v: Indirectly-indexed transposed-RAM of 9-bits pattern
  • iitram9bx1k.v: Indirectly-indexed transposed-RAM of 9-bits pattern / 1K addresses
  • mwm20k.v: Altera's M20K mixed width RAM
  • pe_bhv.v: behavioural description of priority enconder
  • setram.v: Sets RAM
  • vacram.v: Vacancy RAM
  • sim.res: A list of simulation results, each run in a separate line, including all architectures.
  • syn.res: A list of synthesis results, each run in a separate line, including: frequency, resources usage, and runtime.
  • log/: A directory containing Altera's logs and reports.