Group 2: Julia Bi (605502913), Sophia Du (605599095)

I. Introduction

A Phase-Locked Loop (PLL) is a negative feedback circuit that replicates the phase and frequency of an input reference signal. The PLL compares the phase of the input signal to the phase of a generated output signal and adjusts the output frequency so that the signals are in phase, thus "locking" the phase of the output to the input. Since the phase difference is constant, the input and output frequencies are equalized [1].

PLLs are commonly used in integrated circuits for a variety of applications, from clock generation in microprocessors to high speed communication [2].

II. History

Phase-locked loops were first described in 1932 by Henri de Bellescize in a paper published in French journal L'Onde Électrique. It was proposed as a method to stabilize oscillator frequencies. The concept was used in the 1930s in analog television receivers, synchronizing vertical and horizontal sweep circuits to video signals [3]. There was also continuing interest in synchronization due to usage in local oscillators in FM demodulation and atomic particle accelerator amplifiers. In the 1950s, analog phase-locked loops were mainly used to increase power level and attenuate noise in FM signal receivers, reduce the frequency noise of high powered oscillators, and as narrow bandwidth filters [4].

In 1969, American electronics manufacturer Signetics Corporation developed an integrated circuit version of a phase-locked loop using BJTs, bypassing the original issue of high complexity and leading to phase-locked loops becoming more practical and widespread, especially in communications systems [3][5]. Phase locking was used in military and space applications, as well as consumer electronic products. Around this time, digital phase-locked loops were also used as a critical building block for digital communications and tracking receivers [6].

III. Structure

A basic PLL structure consists of three main building blocks in a negative feedback loop: a phase detector (PD), a low pass filter (LPF), and a voltage controlled oscillator (VCO).

A. Phase Detector

A phase detector (PD) compares the phase of the PLL input signal with the phase of the output signal and generates an error signal. One simple example of a phase detector is an exclusive OR (XOR) gate [2]. As seen in Figure 2, when there is a nonzero phase or frequency difference (input and output signals are not equal for a certain period of time), the output of the XOR gate is high. This XOR gate PD detects errors on both the rising and falling edges of the signals; other PD circuits may detect only rising or only falling edge errors.

B. Low Pass Filter

The average voltage of the phase detector output is linearly proportional to the phase difference between the PLL input and output [2]. This average phase error value must be extracted to control the generation of the output frequency. A low pass filter (LPF) is used after the PD to obtain the DC component of the PD output and remove any high frequency noise present.

C. Voltage Controlled Oscillator

A voltage controlled oscillator (VCO) is an oscillator that generates a signal whose frequency is proportional to a control voltage. In a PLL, this control voltage is the filtered phase detector output from the LPF.

When there is a phase difference between the PLL input and output signals, the average of the PD output increases, which increases the VCO control voltage after some delay. This causes the frequency of the VCO to become higher than the input signal, which gradually reduces the phase error (Figure 3). After a certain period of time, the output phase syncs up with the input phase, the PD output average decreases, and the VCO frequency will lower back to the input frequency. A similar process occurs if there is a frequency difference between the PLL input and output signals (Figure 4).

IV. Applications

Phase-locked loops serve to synchronize an internal oscillator to a reference signal, forcing the two to have the same frequency and phase [7]. This avoids the problem of a noisy reference signal causing local amplitude and phase corruption, and is therefore useful in a wide variety of systems which extract or synthesize signals, such as modulators and demodulators, oscillators, synthesizers, and clock signal recovery circuits. Some specific circuits are discussed below.

A. Frequency Multiplication

A phase-locked loop can serve as a frequency synthesizer that generates a high frequency output from a low frequency reference signal. This is often used in microprocessors and has multiple benefits. The cost is generally lower than directly using a high-frequency oscillator component, multiple frequencies can be obtained from one circuit by changing the multiplication factor, and the signal produced is as precise and stable over time and temperature as the reference signal [7].

The system is constructed by adding a frequency divider in the negative feedback path (Figure 5), functioning similarly to an op-amp based non inverting amplifier. If the frequency divider reduces the PLL output frequency by a factor of N, the PLL feedback response will produce an output frequency that is N times higher than the input reference frequency. In most applications, the reference signal is driven by a crystal oscillator, which has low noise. Therefore the system can generate a wide range of frequencies that are multiples of the original frequency, while also maintaining good stability [7].

B. Demodulation of Amplitude-Modulated Signals

One method of demodulating amplitude-modulated (AM) signals is using a system based on a phase locked loop. An additional phase shifter, phase detector, and output filter are added to the original system (Figure 6). This method produces better results than a classic envelope detector, but has higher complexity and cost, so it is not used in most commercial AM radios [8].

C. Demodulation of BPSK Signals

Binary phase shift keying (BPSK) is a type of modulation used in transmission of digital information. The data signal is constructed so that the BPSK signal will have no carrier component at the frequency of a sinusoidal carrier. Therefore, demodulation of the BPSK signal requires a sinusoid with the same phase as the carrier signal [8]. Such a demodulator can be constructed with a squaring loop in which the phase-locked loop acts like a narrowband filter (Figure 7).

D. Phase-Locked Receivers

The Doppler effect causes the frequency of waves to shift based on relative motion of the observer and the source of the wave. A Doppler-shifted signal has an uncertain amount of Doppler shift, causing an uncertainty in signal frequency. One solution to this issue that also produces low noise is a phase-locked receiver, which unlike other methods that utilize a wide bandwidth receiver, can use a bandwidth comparable to that of the signal. Phase-locked receivers are widely used in satellite applications [8].

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VI. References

[1] I. Collins, "Phase-Locked Loop (PLL) Fundamentals," Analog Dialogue, vol. 52, July 2018. [Online]. Available: https://www.analog.com/media/en/analog-dialogue/volume-52/number-3/phase-locked-loop-pll-fundamentals.pdf

[2] B. Razavi, “Phase-Locked Loops,” in Design of Analog CMOS Integrated Circuits, 2nd ed, New York, NY: McGraw-Hill Education, 2017, pp. 651–689

[3] “First Phase-Locked Loop IC,” ISSCC 50th Anniversary Virtual Museum, Lewes, DE: IEEE International Solid-State Circuits Conference, 2003. [Online]. Available: https://sscs.ieee.org/images/files/aboutus/history/ISSCC50/communications/communications_7.pdf

[4] D. R. Stephens, “The Early History of Phase-Locked Loops,” in Phase-Locked Loops for Wireless Communications: Digital and Analog Implementation, New York, NY: Springer Science & Business Media, 1998, pp. 1-8, doi: 10.1007/978-1-4615-5717-3.

[5] A. Grebene and H. Camenzind, "Phase locking as a new approach for tuned integrated circuits," 1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Philadelphia, PA, 1969, pp. 100-101, doi: 10.1109/ISSCC.1969.1154749.

[6] W. C. Lindsey and Chak Ming Chie, "A survey of digital phase-locked loops," in Proceedings of the IEEE, vol. 69, no. 4, 1981, pp. 410-431, doi: 10.1109/PROC.1981.11986.

[7] R. Keim, Understanding PLL Applications: Frequency Multiplication. All About Circuits, 2018. [Online]. Available: https://www.allaboutcircuits.com/technical-articles/understanding-pll-applications-frequency-multiplication/

[8] J. L. Stensby, Phase-Locked Loops: Theory and Applications, Boca Raton, FL: CRC Press, 1997, pp. 3–10.